Metal alloy cap integration
원문보기
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0653665
(2012-10-17)
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등록번호 |
US-8492274
(2013-07-23)
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발명자
/ 주소 |
- Yang, Chih-Chao
- Bergendahl, Marc A.
- Holmes, Steven J.
- Horak, David V.
- Koburger, III, Charles W.
- Ponoth, Shom
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출원인 / 주소 |
- International Business Machines Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
8 인용 특허 :
9 |
초록
▼
A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping
A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap.
대표청구항
▼
1. A method of forming a metal interconnect structure, comprising steps of: forming a liner on top surfaces of a dielectric material and on sidewalls and bottom surfaces of a recessed line pattern in the dielectric material;depositing a copper seed layer on the liner;reflowing the deposited copper s
1. A method of forming a metal interconnect structure, comprising steps of: forming a liner on top surfaces of a dielectric material and on sidewalls and bottom surfaces of a recessed line pattern in the dielectric material;depositing a copper seed layer on the liner;reflowing the deposited copper seed layer on the liner;filling at least a portion of the recessed line pattern with copper;forming an alloy capping layer on the copper comprising an alloying element and copper;reflowing the deposited alloy capping layer on the copper;depositing an electroplated copper layer on the reflowed alloy capping layer;planarizing the electroplated copper layer to the top surfaces of the dielectric material; anddepositing a dielectric cap, wherein the alloy element in the structure is segregated and distributed along an interface between the reflowed copper and the dielectric cap. 2. The method of claim 1 wherein between the steps of planarizing and depositing a dielectric cap, further comprising polishing down to the alloy capping layer at a bottom surface of the electroplated copper layer. 3. The method of claim 1, wherein the alloy capping layer is thin, having a thickness in the range of 1 nm to 6 nm. 4. The method of claim 1, wherein the alloy capping layer is thick, having a thickness in the range of 3 nm to 10 nm, and at least a portion of the alloy capping layer is embedded in the copper material. 5. The method of claim 1, wherein the alloy capping layer is comprised of an alloying element selected from the group of manganese, copper-manganese, cobalt, aluminum, iridium, ruthenium, cobalt-tungsten-phosphorus, platinum and combinations thereof. 6. The method of claim 1, wherein the liner material is comprised of cobalt, ruthenium, iridium, rhodium, platinum, lead, nitrides of any of the foregoing and combinations thereof. 7. The method of claim 1, wherein the recessed line pattern is filled by a reflow annealing process. 8. The method of claim 1, wherein the electroplated copper layer is planarized by a chemical mechanical planarization process. 9. The method of claim 1 wherein there is no alloy element in the copper in the recessed line pattern.
이 특허에 인용된 특허 (9)
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Peijun Ding ; Tony Chiang ; Imran Hashim ; Bingxi Sun ; Barry Chin, Copper alloy seed layer for copper metallization.
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Sudijono, John; Hsia, Liang Ch O; Ping, Liu Wu, Copper recess formation using chemical process for fabricating barrier cap for lines and vias.
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Gardner, Donald S., Copper reflow process.
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Onishi, Takashi; Mizuno, Masao; Takeda, Mikako; Tsukimoto, Susumu; Kabe, Tatsuya; Morita, Toshifumi; Moriyama, Miki; Ito, Kazuhiro; Murakami, Masanori, Fabrication method for semiconductor interconnections.
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Batra, Shubneesh; Sandhu, Gurtej, Low temperature reflow method for filling high aspect ratio contacts.
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Chao-Kun Hu ; Robert Rosenberg ; Judith Marie Rubino ; Carlos Juan Sambucetti ; Anthony Kendall Stamper, Reduced electromigration and stressed induced migration of Cu wires by surface coating.
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Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
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Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD.
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Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
이 특허를 인용한 특허 (8)
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Edelstein, Daniel C.; Nguyen, Son V.; Nogami, Takeshi; Priyadarshini, Deepika; Shobha, Hosadurga K., Copper interconnect structure with manganese oxide barrier layer.
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Edelstein, Daniel C.; Nguyen, Son V.; Nogami, Takeshi; Priyadarshini, Deepika; Shobha, Hosadurga K., Interconnect structure with barrier layer.
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Edelstein, Daniel C.; Nguyen, Son V.; Nogami, Takeshi; Priyadarshini, Deepika; Shobha, Hosadurga K., Interconnect structure with capping layer and barrier layer.
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Yang, Chih-Chao; Bergendahl, Marc A.; Holmes, Steven J.; Horak, David V.; Koburger, Charles W.; Ponoth, Shom, Metal alloy cap integration.
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Edelstein, Daniel C.; Nguyen, Son V.; Nogami, Takeshi; Priyadarshini, Deepika; Shobha, Hosadurga K., Method of forming a copper based interconnect structure.
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Murray, Conal E.; Yang, Chih-Chao, Semiconductor device with reduced via resistance.
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Murray, Conal E.; Yang, Chih-Chao, Semiconductor device with reduced via resistance.
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Murray, Conal E.; Yang, Chih-Chao, Semiconductor device with reduced via resistance.
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