$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Barrier-metal-free copper damascene technology using enhanced reflow 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
출원번호 US-0484824 (2012-05-31)
등록번호 US-8513112 (2013-08-20)
발명자 / 주소
  • Ahn, Kie Y.
  • Forbes, Leonard
출원인 / 주소
  • Mosaid Technologies, Incorporated
대리인 / 주소
    Browdy and Neimark, PLLC
인용정보 피인용 횟수 : 4  인용 특허 : 35

초록

A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and m

대표청구항

1. A method of forming a contact in an opening in an insulative material, comprising: forming a non-metal barrier material over the insulative material within the opening;depositing a conductive material over the non-metal barrier material to fill the opening; andreflowing the conductive material in

이 특허에 인용된 특허 (35)

  1. Farrar Paul A. ; Givens John H., Alloy for enhanced filling of high aspect ratio dual damascene structures.
  2. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  3. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  4. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  5. Ahn, Kie Y.; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  6. Ahn, Kie Y; Forbes, Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  7. Ahn,Kie Y; Forbes,Leonard, Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow.
  8. Lu Toh-Ming (Latham NY) Mei Shao-Ning (Wappingers Falls NY), Deposition of metals on stepped surfaces.
  9. Moradi Behnam ; Raina Kanwal K. ; Westphal Michael J., Field emission display cathode assembly government rights.
  10. Batra Shubneesh ; Sandhu Gurtej, Low temperature reflow method for filling high aspect ratio contacts.
  11. Forbes Leonard ; Noble Wendell P., Memory address decode array with vertical transistors.
  12. Grabarz Henry J. (Huntington CT) Grill Alfred (White Plains NY) Holber William M. (New York NY) Logan Joseph S. (Poughkeepsie NY) Yeh James T. C. (Katonah NY), Method and apparatus for filing high aspect patterns with metal.
  13. Somekh Sasson (Los Altos Hills CA) Nulman Jaim (Palo Alto CA) Chang Mei (Cupertino CA), Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer.
  14. Ahn Kie Y., Method of fabricating integrated circuit wiring with low RC time delay.
  15. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of forming a smooth copper seed layer for a copper damascene structure.
  16. Baumgart Helmut (Mahopac NY) Martinez Andre (Derry NH), Method of forming improved encapsulation layer.
  17. Forbes Leonard ; Farrar Paul A. ; Ahn Kie Y., Methods and structures for gold interconnections in integrated circuits.
  18. Ahn Kie Y. ; Forbes Leonard, Methods for making copper and other metal interconnections in integrated circuits.
  19. Ahn Kie Y. ; Forbes Leonard, Multichip module with built in repeaters and method.
  20. Kim Edwin ; Nam Michael ; Cha Chris ; Yao Gongda ; Lee Sophia ; Dorleans Fernand ; Kohara Gene Y. ; Fu Jianming, Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers.
  21. Takamatsu Toshiyuki,JPX ; Fujimura Shuzo,JPX, Plasma surface treatment method and resulting device.
  22. Nieh Simon K. (Monrovia CA) Matossian Jesse N. (Canoga Park CA) Krajenbrink Frans G. (Newbury Park CA), Plasma-enhanced magnetron-sputtered deposition of materials.
  23. Cathey ; Jr. David A. (Boise ID), Process for fabricating conductors used for integrated circuit connections and the like.
  24. Jain Ajay, Process for forming a semiconductor device.
  25. Tokunaga Takafumi (Tokorozawa JPX) Tsuneoka Masatoshi (Ohme JPX) Mizukami Koichiro (Akishima JPX), Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device.
  26. Gardner Donald S., Rapid reflow of conductive layers by directional sputtering for interconnections in integrated circuits.
  27. Kaoru Mikagi JP, Semiconductor device and method for making the same.
  28. Mikagi Kaoru,JPX, Semiconductor device and method for making the same.
  29. Takagi Hideo,JPX ; Uji Shigetaka,JPX ; Hirao Shyoji,JPX, Semiconductor device manufacturing method.
  30. Hamamoto Takeshi (Kawasaki JPX) Horiguchi Fumio (Tokyo JPX) Hieda Katsuhiko (Yokohama JPX), Semiconductor memory with pad electrode and bit line under stacked capacitor.
  31. Richard J. Huang ; Guarionex Morales ; Simon Chan, Surface treatment of low-K SiOF to prevent metal interaction.
  32. Huang Richard J. ; Morales Guarionex ; Chan Simon, Surface treatment of low-k SiOF to prevent metal interaction.
  33. Forbes Leonard ; Ahn Kie Y., Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits.
  34. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
  35. Gardner Donald S. (Mountain View CA), Wetting layer sidewalls to promote copper reflow into grooves.

이 특허를 인용한 특허 (4)

  1. Lee, Soogeun, Cost effective method of forming embedded DRAM capacitor.
  2. Adusumilli, Praneet; Reznicek, Alexander; van der Straten, Oscar, Reflow enhancement layer for metallization structures.
  3. Adusumilli, Praneet; Reznicek, Alexander; van der Straten, Oscar, Reflow enhancement layer for metallization structures.
  4. Chapple-Sokol, Jonathan D.; Christiansen, Cathryn J.; Gambino, Jeffrey P.; Lee, Tom C.; Murphy, William J.; Stamper, Anthony K., Titanium tungsten liner used with copper interconnects.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로