Computers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewalls
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-015/16
G06F-009/00
출원번호
US-0180164
(2011-07-11)
등록번호
US-8516033
(2013-08-20)
발명자
/ 주소
Ellis, III, Frampton E.
출원인 / 주소
Ellis, III, Frampton E.
대리인 / 주소
DLA Piper LLP US
인용정보
피인용 횟수 :
1인용 특허 :
178
초록▼
A personal computer or microchip comprising: a primary internal hardware firewall separating a protected side of the computer's hardware from a network side connected to a network of computers; a master controller and/or a microprocessor is located within the hardware protected side protected by the
A personal computer or microchip comprising: a primary internal hardware firewall separating a protected side of the computer's hardware from a network side connected to a network of computers; a master controller and/or a microprocessor is located within the hardware protected side protected by the primary internal hardware firewall; microprocessors are located within the network side located between the primary internal hardware firewall and the network connection; the network side microprocessors are separate components from the primary internal hardware firewall; the primary internal hardware firewall by its internal location not restricting access by the network to the computer's network side, thereby not restricting the network operations of the computer, which are conducted in the network side using the networked microprocessors; and one or more secondary interior hardware firewalls form one or more separate hardware protected compartments in the hardware protected side, a compartment including for example a hardware protected microprocessor.
대표청구항▼
1. A personal computer configured for use by at least one individual user, said computer comprising: at least a primary internal hardware firewall configured to protect a hardware protected side of the computer's hardware from a network side that is not protected by said primary internal hardware fi
1. A personal computer configured for use by at least one individual user, said computer comprising: at least a primary internal hardware firewall configured to protect a hardware protected side of the computer's hardware from a network side that is not protected by said primary internal hardware firewall, at least one microprocessor and at least a non-volatile memory is located within said hardware protected side;one or more network side microprocessors with at least a volatile memory and at least one network communications component are located within said network side, said network side being configured for connection to the network of computers and being located between said primary internal hardware firewall and a wired or wireless network connection to said network of computers; said one or more network side microprocessors being separate components from said at least one network communications component, and both said network side microprocessors and said at least one network communication component being separate from said primary internal hardware firewall;said primary internal firewall by its internal location not restricting access by the network to the network side, thereby not restricting the network operations of the computer, which are conducted in said network side using said network side microprocessors;at least a first secondary interior hardware firewall configured to form a first separate hardware protected compartment located in said hardware protected side; and at least one hardware protected side microprocessor with at least a non-volatile memory is located in said first separate hardware protected compartment located in said hardware protected side. 2. The computer of claim 1, wherein said first secondary interior hardware firewall is configured to deny access to said first separate hardware protected compartment by said network. 3. The computer of claim 1, further comprising a second said secondary interior hardware firewall configured to form a second said separate hardware protected compartment located in said first separate hardware protected compartment; and at least one hardware protected side microprocessor with at least a non-volatile memory is located in said second separate hardware protected compartment. 4. The computer of claim 3, wherein said second secondary interior hardware firewall is configured to deny access to said second separate hardware protected compartment by said network. 5. The computer of claim 3, further comprising a third said secondary interior hardware firewall configured to form a third said separate hardware protected compartment located in said second separate hardware protected compartment; and at least one said hardware protected side microprocessor with at least a non-volatile memory is located in said third separate hardware protected compartment. 6. The computer of claim 5, wherein said third secondary interior hardware firewall is configured to deny access to said third separate hardware protected compartment by said network. 7. The computer of claim 5, further comprising a fourth said secondary interior hardware firewall configured to form a fourth said separate hardware protected compartment located in said third separate hardware protected compartment; and at least one said hardware protected side microprocessor with at least a non-volatile memory is located in said fourth separate hardware protected compartment. 8. The computer of claim 7, wherein said fourth secondary interior hardware firewall is configured to deny access to said fourth separate hardware protected compartment by said network. 9. The computer of claim 7, further comprising at least four additional said secondary interior hardware firewalls configured to form at least four additional said separate hardware protected compartments located in said hardware protected side; and at least four additional said hardware protected side microprocessors, each with at least a volatile memory and each located in a separate one of said four additional separate hardware protected compartments located in said hardware protected side. 10. The computer of claim 7, further comprising a master controlling device located in said fourth separate hardware protected compartment located in said hardware protected side. 11. The computer of claim 5, further comprising a master controlling device located in said third separate hardware protected compartment located in said hardware protected side. 12. The computer of claim 3, further comprising a master controlling device located in said second separate hardware protected compartment located in said hardware protected side. 13. The computer of claim 1, further comprising a master controlling device located in said first separate hardware protected compartment located in said hardware protected side. 14. The computer of claim 1, further comprising a second said secondary interior hardware firewall configured to form a second said separate hardware protected compartment located in said network side; and at least one microprocessor is located in said second separate hardware protected compartment located in said network side. 15. The computer of claim 14, further comprising a third said secondary interior hardware firewall configured to form a third said separate hardware protected compartment located in said network side; and at least one microprocessor is located in said third separate hardware protected compartment located in said network side. 16. The computer of claim 14, wherein at least one network user utilizes at least one of said network side microprocessors located in at least one said separate hardware protected compartment located in said network side. 17. The computer of claim 1, further comprising at least four additional said secondary interior hardware firewalls configured to form at least four additional said separate hardware protected compartments located in said network side; and at least four additional microprocessors, each is located in one said additional separate hardware protected compartment located in said network side. 18. The computer of claim 1, further comprising a hardware memory component with an internal hardware firewall configured to protect a hardware protected side of the hardware memory component from a network side of the hardware memory component, said network side of said hardware memory component not being protected by said internal hardware firewall of said hardware memory component. 19. The computer of claim 1, wherein the network operations of the computer are conducted only in the network side using said network side microprocessors. 20. The computer of claim 1, wherein said at least one network communications component includes at least a digital signal processor or a modem. 21. The computer of claim 1, wherein the computer is a node in an array of other computers linked together as nodes to form a server and/or a mainframe and/or a supercomputer. 22. The computer of claim 1, further comprising a memory component of the computer located in at least one said separate hardware protected compartment that is located in the hardware protected side of the computer's hardware, said separate hardware protected compartment being protected at least by an additional said secondary interior hardware firewall. 23. The computer of claim 1, wherein at least a portion of the files of at least one operating system of the computer is located inside each of at least three additional said separate hardware protected compartments, each said additional said separate hardware protected compartment being protected by at least a separate secondary inner hardware firewall. 24. The computer of claim 1, wherein at least a portion of the files of at least one software application of the computer is located inside each of at least three additional said separate hardware protected compartments, each said additional said separate hardware protected compartment being protected by at least a separate secondary inner hardware firewall. 25. The computer of claim 1, wherein at least a portion of the files of at least one user of the computer is located inside each of at least three additional said separate hardware protected compartments, each said additional said separate hardware protected compartment being protected by at least a separate secondary inner hardware firewall. 26. The computer of claim 1, wherein said hardware protected side includes at least one master controlling device of the computer. 27. The computer of claim 1, wherein said computer is configured to be a node in an array of other said computers as nodes linked together to form a server and/or a mainframe and/or a supercomputer. 28. The computer of claim 1, wherein said computer comprises a microchip configured for use in a personal computer by at least one individual user, said microchip comprising at least said microprocessor, at least said primary internal hardware firewall and at least said first secondary interior hardware firewall. 29. A microchip configured for use in a personal computer by at least one individual user, said microchip comprising: a microprocessor, the microprocessor including at least two processing units; andat least a primary internal hardware firewall is configured to protect a hardware protected side of the microchip's hardware from a network side that is not protected by said primary internal hardware firewall, at least one of the processing units of the microprocessor is located within said hardware protected side;one or more of the processing units of the microprocessor is located within said network side, and said network side being configured for connection to the network of computers and being located between said primary internal hardware firewall and a wired or wireless network connection to said network of computers; said one or more network side processing units being separate from said primary internal hardware firewall;said primary internal firewall by its internal location not restricting access by the network to the unprotected network side of the microchip, thereby not restricting the network operations of the microchip, which are conducted in said network side using said network side processing units of the microchip;at least a first secondary interior hardware firewall is configured to form at least a first separate hardware protected compartment located in the hardware protected side; and at least one hardware protected side processing unit is located in said at least one separate hardware protected compartment located in said hardware protected side. 30. The microchip of claim 29, wherein the network operations of the computer are conducted only in the network side using said network side microprocessors. 31. The microchip of claim 29, wherein at least one network communications component is located in said network side. 32. The microchip of claim 31, wherein said at least one network communications component located in said network side includes at least a digital signal processor or a modem. 33. The microchip of claim 29, wherein said hardware protected side includes at least a non-volatile memory and said network side includes at least a volatile memory. 34. The microchip of claim 29, wherein said first secondary interior hardware firewall is configured to deny access to said first separate hardware protected compartment by said network. 35. The microchip of claim 29, further comprising a second said secondary interior hardware firewall configured to form a second said separate hardware protected compartment located in said first separate hardware protected compartment; and at least one hardware protected side microprocessor with at least a non-volatile memory is located in said second separate hardware protected compartment. 36. The microchip of claim 35, wherein said second secondary interior hardware firewall is configured to deny access to said second separate hardware protected compartment by said network. 37. The microchip of claim 35, further comprising a third said secondary interior hardware firewall configured to form a third said separate hardware protected compartment located in said second separate hardware protected compartment; and at least one said hardware protected side microprocessor with at least a non-volatile memory is located in said third separate hardware protected compartment. 38. The microchip of claim 37, wherein said third secondary interior hardware firewall is configured to deny access to said third separate hardware protected compartment by said network. 39. The microchip of claim 38, further comprising a fourth said secondary interior hardware firewall configured to form a fourth said separate hardware protected compartment located in said third separate hardware protected compartment; and at least one said hardware protected side microprocessor with at least a non-volatile memory is located in said fourth separate hardware protected compartment. 40. The microchip of claim 39, wherein said fourth secondary interior hardware firewall is configured to deny access to said fourth separate hardware protected compartment by said network. 41. The microchip of claim 39, further comprising at least four additional said secondary interior hardware firewalls configured to form at least four additional said separate hardware protected compartments located in said hardware protected side; and at least four additional said hardware protected side microprocessors, each with at least a volatile memory and each located in a separate one of said four additional separate hardware protected compartments located in said hardware protected side. 42. The microchip of claim 39, further comprising a master controlling device located in said fourth separate hardware protected compartment located in said hardware protected side. 43. The microchip of claim 37, further comprising a master controlling device located in said third separate hardware protected compartment located in said hardware protected side. 44. The microchip of claim 35, further comprising a master controlling device located in said second separate hardware protected compartment located in said hardware protected side. 45. The microchip of claim 29, further comprising a master controlling device located in said first separate hardware protected compartment located in said hardware protected side. 46. The microchip of claim 29, further comprising a second said secondary interior hardware firewall configured to form a second said separate hardware protected compartment located in said network side; and at least one microprocessor is located in said second separate hardware protected compartment located in said network side. 47. The microchip of claim 46, further comprising a third said secondary interior hardware firewall configured to form a third said separate hardware protected compartment located in said network side; and at least one microprocessor is located in said third separate hardware protected compartment located in said network side. 48. The microchip of claim 46, wherein at least one network user utilizes at least one of said network side microprocessors located in at least one said separate hardware protected compartment located in said network side. 49. The microchip of claim 29, further comprising at least four additional said secondary interior hardware firewalls configured to form at least four additional said separate hardware protected compartments located in said network side; and at least four additional microprocessors, each is located in one said additional separate hardware protected compartment located in said network side. 50. The microchip of claim 29, further comprising a hardware memory component with an internal hardware firewall configured to protect a hardware protected side of the hardware memory component from a network side of the hardware memory component, said network side of said hardware memory component not being protected by said internal hardware firewall of said hardware memory component. 51. The microchip of claim 29, wherein the microchip is a node in an array of computers linked together as nodes to form a server and/or a mainframe and/or a supercomputer. 52. The microchip of claim 29, further comprising a memory component of the microchip located in at least one said separate hardware protected compartment that is located in the hardware protected side of the microchip's hardware, said separate hardware protected compartment being protected at least by an additional said secondary interior hardware firewall. 53. The microchip of claim 29, wherein at least a portion of the files of at least one operating system of the microchip is located inside each of at least three additional said separate hardware protected compartments, each said additional said separate hardware protected compartment being protected by at least a separate secondary inner hardware firewall. 54. The microchip of claim 29, wherein at least a portion of the files of at least one software application of the microchip is located inside each of at least three additional said separate hardware protected compartments, each said additional said separate hardware protected compartment being protected by at least a separate secondary inner hardware firewall. 55. The microchip of claim 29, wherein said hardware protected side includes at least one master controlling unit of the microchip. 56. The microchip of claim 29, wherein said microchip is in a computer configured to be a node in an array of other said computers as nodes linked together to form a server and/or a mainframe and/or a supercomputer. 57. The microchip of claim 29, wherein at least a portion of the files of at least one user of the computer is located inside each of at least three additional said separate hardware protected compartments, each said additional said separate hardware protected compartment being protected by at least a separate secondary inner hardware firewall. 58. A personal computer configured for use by at least one individual user, said personal computer including a microchip and at least one separate network communications component, said microchip comprising: a microprocessor, the microprocessor including at least two processing units; andat least a primary internal hardware firewall configured to protect a hardware protected side of the microchip's hardware from a network side of the microchip, said network side is not protected by said primary internal hardware firewall, at least one of the processing units of the microprocessor is located within said hardware protected side;one or more of the processing units of the microprocessor is located within said network side, and said network side is configured for connection to the network of computers and being located between said primary internal hardware firewall and a wired or wireless network connection to said network of computers; said one or more network side processing units being separate from said primary internal hardware firewall;said primary internal firewall by its location does not restrict access by the network to said network side of the microchip, thereby enabling network operations between the microchip and the network to be conducted in said network side using said network side processing units of the microchip;at least one secondary inner hardware firewall is configured to form at least one separate hardware protected compartment located in the network side; andat least one said network side processing unit is located in said at least one separate hardware protected compartment located in said network side. 59. The personal computer of claim 58, wherein said hardware protected side includes a master controlling unit.
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Nielsen Keith E. (Redondo Beach CA), Active energy control for diode pumped laser systems using pulsewidth modulation.
Benkeser Donald E. (Naperville IL) Cyr Joseph B. (Aurora IL) Greenberg Albert G. (Millburn NJ) Wright Paul E. (Basking Ridge NJ), Adaptive job scheduling for multiprocessing systems with master and slave processors executing tasks with opposite antic.
Bonneau ; Jr. Walt C. (Missouri City TX) Guttag Karl (Missouri City TX) Gove Robert (Dallas TX), Architecture of a chip having multiple processors and multiple memories.
Russell David S. (Minneapolis MN) Fischer Larry G. (Waseca MN) Wala Philip M. (Waseca MN) Ratliff Charles R. (Crystal Lake IL) Brennan Jeffrey (Waseca MN), Cellular communications system with centralized base stations and distributed antenna units.
Naedel Richard G. (Rockville MD) Harris David B. (Columbia MD) Uehling Mark (Bowie MD), Chassis and personal computer for severe environment embedded applications.
Berkowitz David B. (Palo Alto CA) Hao Ming C. (Los Altos CA) Lieu Hung C. (Santa Clara CA) Snow Franklin D. (Saratoga CA), Collaborative computing system using pseudo server process to allow input from different server processes individually a.
Sumimoto Shinji (Kawasaki JPX), Computer resource distributing method and system for distributing a multiplicity of processes to a plurality of computer.
Passera Anthony ; Thorp John R. ; Beckerle Michael J. ; Zyszkowski Edward S. A., Computer system and computerized method for partitioning data for parallel processing.
Jones Oliver (Andover MA) Deshon Mary (Winthrop MA) Ericsson Staffan (Brookline MA) Flach James (Cave Creek AZ), Computer teleconferencing method and apparatus.
Ellis, III, Frampton E., Computers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartments.
Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall and an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary inner hardware firewalls.
Glick James A. (Granite Shoals TX) Graczyk Ronald B. (Round Rock TX) Nurick Albert F. (Austin TX) Fraley Brittain D. (Austin TX), Computing and multimedia entertainment system.
Leung Wing Y. (Cupertino CA) Hsu Fu-Chieh (Saratoga CA), Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale in.
Morley Richard E. (Greenville NH), Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and met.
Bruckert William F. (Northboro MA) Bissett Thomas D. (Derry NH) Riegelhaupt Norbert H. (Framingham MA), Dual-rail processor with error checking at single rail interfaces.
Rosenberry Steven (Reading PA), Dynamic fault-tolerant parallel processing system for performing an application function with increased efficiency using.
Pian Chao-Kuang (Anaheim CA) Habereder Hans L. (Orange CA), Dynamic task allocation in a multi-processor system employing distributed control processors and distributed arithmetic.
Pezeshki Bardia (Huntington Beach CA) Harris ; Jr. James S. (Stanford CA), Electrostatically tunable optical device and optical interconnect for processors.
Wilkinson Paul Amba ; Dieffenderfer James Warren ; Kogge Peter Michael ; Schoonover Nicholas Jerome, Fully scalable parallel processing system having asynchronous SIMD processing.
Nguyen Tam M. (Valhalla NY) Rana Deepak (Yorktown Heights NY) Ruiz Antonio (Yorktown Heights NY) Willner Barry E. (Briarcliff Manor NY), Hybrid digital/analog multimedia hub with dynamically allocated/released channels for video processing and distribution.
Fucito Michele (Meta ITX) Recchia Maruo (Rome ITX) Puglia Silvestro (Pomezia ITX) Mariani Claudio (Rome ITX) Colangeli Giulio (Gerenzano di Roma ITX) Rotunno Antonio (Salerno ITX), Interface unit for dynamically configuring a buffer in different modes to store data transfers based upon different conn.
Guy Charles B. (Hillsboro OR) Cadambi Sudarshan B. (Beaverton OR) Gutmann Michael J. (Portland OR) Bhasker Narjala (Portland OR) Trethewey Jim R. (Beaverton OR) McArdle Brian J. (Beaverton OR), Interrupt distribution scheme for a computer bus.
Wade Jon P. ; Cassiday Daniel R. ; Lordi Robert D. ; Steele ; Jr. Guy Lewis ; St. Pierre Margaret A. ; Wong-Chan Monica C. ; Abuhamdeh Zahi S. ; Douglas David C. ; Ganmukhi Mahesh N. ; Hill Jeffrey V, Massively parallel computer including auxiliary vector processor.
Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L., Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network an.
Bruckert William (Northboro MA) Kovalcin David (Grafton MA) Bissett Thomas D. (Derry NH) Munzer John (Brookline MA) Mazur Dennis (Worcester MA) Mott ; Jr. Peter R. (Worcester MA) Dearth Glenn A. (Hud, Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having.
Ault Donald Fred ; Bender Ernest Scott ; Spiegel Michael Gary, Method and apparatus for creating a security environment for a user task in a client/server system.
Kisor Greg, Method and system including a central computer that assigns tasks to idle workstations using availability schedules and computational capabilities.
Farnworth Warren M. (Boise ID) Duesman Kevin (Boise ID) Heitzeberg Ed (Boise ID), Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers.
Rausch Dieter (Karlsruhe DEX), Method for preventing an overload when starting a multicomputer system and multicomputer system for carrying out said me.
Shorter David U. (Lewisville TX), Method for scheduling execution of distributed application programs at preset times in an SNA LU 6.2 network environment.
Harris Jonathan P. (Littleton MA) Leibholz Daniel (Watertown MA) Miller Brad (Westborough MA), Method of dynamically allocating processors in a massively parallel processing system.
Ellis, Frampton E., Method of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Ellis, Frampton E., Methods of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
Hu Ming K. (Syracuse NY) Jia Yau G. (Nanjing ; Jiangsu CNX), Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors.
Barker Thomas Norman ; Collins Clive Allan ; Dapp Michael Charles ; Dieffenderfer James Warren ; Knowles Billy Jack ; Rolfe David Bruce, N-dimensional modified hypercube.
Hodge Winston W. (Yorba Linda CA) Taylor Lawrence E. (Anaheim CA), Near-video-on-demand digital video distribution system utilizing asymmetric digital subscriber lines.
Georgiou,Christos J.; Gregurick,Victor L.; Nair,Indira; Salapura,Valentina, Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus.
Hinsley Christopher Andrew,GBX, Operating system for use with computer networks incorporating one or more data processors linked together for parallel p.
Chin Danny (Robbinsville NJ) Sauer Donald J. (Allentown NJ) Meyerhofer Dietrich (Princeton NJ) Katsuki Kazuo (Hyogo JPX), Parallel digital processing system using optical interconnection between control sections and data processing sections.
Beatty Harry J. (Clinton Corners NY) Elmendorf Peter C. (Kingston NY) Gillis Roland R. (Ulster Park NY) Pramanick Ira (Wappingers Falls NY), Parallel execution of a complex task partitioned into a plurality of entities.
Beatty Harry John ; Elmendorf Peter Claude ; Gillis Roland Roberto ; Pramanick Ira, Parallel execution of a complex task partitioned into a plurality of entities.
Bahr James E. (Rochester MN) Corrigan Michael J. (Rochester MN) Knipfer Diane L. (Rochester MN) McMahon Lynn A. (Rochester MN) Metzger Charlotte B. (Elgin MN), Process for dispatching tasks among multiple information processors.
Nelson Darul J. ; Noval James V. ; Suarez Ricardo E. ; Aghazadeh Mostafa A., Processor card assembly including a heat sink attachment plate and an EMI/ESD shielding cage.
Gregerson Daniel P. ; Farrell David R. ; Gaitonde Sunil S. ; Ahuja Ratinder P. ; Ramakrishnan Krish ; Shafiq Muhammad ; Wallis Ian F., Scalable distributed computing environment.
Ohta Hiroyuki,JPX ; Miura Hideo,JPX ; Usami Mitsuo,JPX ; Kametani Masatsugu,JPX ; Zen Munetoshi,JPX ; Okamoto Noriaki,JPX, Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same.
Danahy John J. ; Kinney Daryl F. ; Pulsinelli Gary S. ; Rose Lawrence J. ; Kumar Navaneet, Service-centric monitoring system and method for monitoring of distributed services in a computing network.
Hoover Russell D. (Rochester MN) Willis John C. (Rochester MN) Baldus Donald F. (Mazeppa MN) Ziegler Frederick J. (Rochester MN) Liu Lishing (Pleasantville NY), System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data p.
Teper Jeffrey A. ; Koneru Sudheer ; Mangione Gordon ; Balaz Rudolph ; Contorer Aaron M. ; Chao Lucy, System and method for providing trusted brokering services over a distributed network.
Chasek Norman E. (24 Briar Brae Rd. Stamford CT 06903), System for developing real time economic incentives to encourage efficient use of the resources of a regulated electric.
Leclercq Thierry (Paris FRX) Sallio Patrick (Thorigne-Fouillard FRX), System for management of the usage of data consultations in a telecommunication network.
Choquier Philippe,FRX ; Peyroux Jean-Francios ; Griffin William J., System for on-line service in which gateway computer uses service map which includes loading condition of servers broad.
Baehr Geoffrey G. ; Danielson William ; Lyon Thomas L. ; Mulligan Geoffrey ; Patterson Martin,FRX ; Scott Glenn C. ; Turbyfill Carolyn, System for packet filtering of data packets at a computer network interface.
Shwed Gil,ILX ; Kramer Shlomo,ILX ; Zuk Nir,ILX ; Dogon Gil,ILX ; Ben-Reuven Ehud,ILX, System for securing the flow of and selectively modifying packets in a computer network.
Padgaonkar Ajay J. (Phoenix AZ) Mitra Sumit K. (Tempe AZ), System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory.
Kraft Reiner ; Lu Qi ; Wisebond Marat, Task distribution processing system and the method for subscribing computers to perform computing tasks during idle time.
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