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A program data area 38 storing program data is provided in an internal memory unit that a control circuit 31 of a CPU 3 can directly red from. The program data is constituted by instructions each comprising an instruction information part and an operand (i.e., a complementary information part) for u

A program data area 38 storing program data is provided in an internal memory unit that a control circuit 31 of a CPU 3 can directly red from. The program data is constituted by instructions each comprising an instruction information part and an operand (i.e., a complementary information part) for use in execution of this instruction information part. The program data area 38 comprises a plurality of 24-bit data areas each having an address indicative thereof. One instruction is stored in one data area such that the instruction information part resides at the beginning of the data area.

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1. A central processing unit, comprising a control circuit for reading a program data from an internal memory unit and executing the program data, the program data being variable-length instructions that include an instruction information part and a complementary information part for execution of th

1. A central processing unit, comprising a control circuit for reading a program data from an internal memory unit and executing the program data, the program data being variable-length instructions that include an instruction information part and a complementary information part for execution of the instruction information part, wherein: (A) the internal memory unit includes a plurality of data areas each having a predetermined capacity and an address, the internal memory unit being directly read by the control circuit, (B) the instructions are stored in the data areas on a one-to-one basis and the instruction information parts red in same locations at or away from a predefined extent from beginning of the corresponding data areas, and (C) the program data is pre-stored in the internal memory unit prior to start-up of the central processing unit such that the variable-length instructions are in accordance with storage format of the internal memory unit. 2. A microcontroller comprising: (a) the central processing unit of claim 1; and(b) an external memory unit connected to the central processing unit via an address bus and a data bus, the address bus including a read address bus and a write address bus; the data bus including a read data bus and a write data bus; the central processing unit being configured to output, on the read address bus, an address at which a read data to be read is stored so as to read the read data from the external memory unit; the central processing unit being configured to output, on the write address bus, another address at which a write data is to be written in the external memory, and output the write data on the write data bus so as to write the write data into the external memory unit; the external memory unit being configured to output the read data on the read data bus, the read data residing at the address that has been input via the read address bus into the external memory unit; and the external memory unit being configured to write the data that has been input via the write data bus into the external memory at the other address that has been input via the write address bus. 3. The central processing unit according to claim 1, wherein the control unit is connected via internal bus to the internal memory unit so that the internal memory unit is directly read by the control circuit. 4. The central processing unit according to claim 1, wherein the control unit uses as an IR register beginning fields of the data areas of the internal memory unit so as to directly read the internal memory unit. 5. The central processing unit according to claim 1, wherein one instruction can be executed upon one round of increasing of a PC register.