초록 ▼

An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator lay

An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.

대표청구항 ▼

1. A method of forming a semiconductor-on-insulator structure comprising: providing a semiconductor-on-insulator substrate including a stack, from bottom to top, of a base substrate, a buried insulator layer, and a top semiconductor active layer, wherein an interface is present between a topmost sur

1. A method of forming a semiconductor-on-insulator structure comprising: providing a semiconductor-on-insulator substrate including a stack, from bottom to top, of a base substrate, a buried insulator layer, and a top semiconductor active layer, wherein an interface is present between a topmost surface of said buried insulator layer and a bottommost surface of said top semiconductor active layer;forming a least one semiconductor device-containing region comprising at least one semiconductor device formed on and/or within a portion of said top semiconductor active layer;providing at least a stressor layer on an exposed surface of said at least one semiconductor device-containing region, wherein said stressor layer has a fracture toughness that is greater than that of said base substrate; andremoving a material base layer from said base substrate by spalling, wherein said material base layer is located on a bottommost surface of said buried insulator layer; andimplanting ions into said buried insulator layer though said bottommost surface of the buried insulator layer that is opposite the topmost surface of the buried insulator layer that forms the interface with said top semiconductor active layer to provide a radiation hardened structure comprising said buried insulator layer that includes a doped region and a substantially non-doped region, wherein said substantially non-doped region has a surface in contact with said interface. 2. The method of claim 1, wherein a portion of said material base layer remains on the bottommost surface of the buried insulator layer during said implanting ions. 3. The method of claim 1, further comprising reducing a thickness of said material base layer prior to said implanting ions. 4. The method of claim 3, wherein said reducing the thickness of said material base layer comprises etching or combination of oxidation and etching. 5. The method of claim 1, wherein said material base layer is completely removed from said bottommost surface of said buried insulator layer prior to said implanting ions. 6. The method of claim 1, further comprising applying a flexible handle substrate on an exposed surface of said stressor layer prior to removing said material base layer by spalling. 7. The method of claim 1, wherein said providing the stressor layer comprises selecting a metal, a polymer or any combination. 8. The method of claim 7, wherein said providing the stressor layer comprises selecting a spall inducing tape as said polymer. 9. The method of claim 1, wherein said providing the stressor layer comprises selecting Ni as a stress inducing layer and applying a flexible handle layer on an exposed surface of said Ni. 10. The method of claim 1, wherein said spalling is performed at room temperature or a temperature of less than room temperature. 11. The method of claim 1, wherein said implanting ions comprise selecting an ion selected from the group consisting of boron, silicon, germanium, aluminum, arsenic, nitrogen and mixtures thereof. 12. The method of claim 11, wherein said selected ion is implanted at a dose from 1013 atoms/cm2 to 1016 atoms/cm2. 13. The method of claim 1, wherein said implanting ions comprise selecting a heavy ion selected from the group consisting of argon, germanium, and xenon. 14. The method of claim 13, wherein said selected heavy ion is implanted at a dose from 1011 atoms/cm2 to 1016 atoms/cm2. 15. The method of claim 1, further comprising bonding an exposed surface of said radiation hardened structure to a handle substrate. 16. The method claim 1, wherein said doped region is located beneath said substantially non-doped region and no portion of said doped region contacts said topmost surface of said buried insulator layer. 17. The method of claim 1, further comprising removing at least said stressor layer from atop the at least one semiconductor device-containing region after said implanting ions. 18. The method of claim 1, wherein said top semiconductor active layer is a single crystal Si-containing semiconductor material, and said base substrate is a semiconductor material. 19. The method of claim 1, further comprising forming at least one of a metal-containing adhesion layer and a plating seed layer prior to providing the stressor layer. 20. The method of claim 1, wherein said substantially non-doped region has a thickness extending from the topmost surface of the buried insulator layer inward of greater than 5 nm.