IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0458196
(2012-04-27)
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등록번호 |
US-8519466
(2013-08-27)
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발명자
/ 주소 |
- Forbes, Leonard
- Ahn, Kie Y.
- Bhattacharyya, Arup
|
출원인 / 주소 |
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대리인 / 주소 |
Schwegman, Lundberg & Woessner, P.A.
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인용정보 |
피인용 횟수 :
0 인용 특허 :
213 |
초록
▼
Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be for
Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.
대표청구항
▼
1. An electronic device comprising: a substrate;a dielectric disposed on the substrate, the dielectric including TaxSiyOzNr (x, y, z, r>0) structured as an arrangement of one or more monolayers, wherein the dielectric is structured as a tunnel gate insulator in a vertical floating gate transistor an
1. An electronic device comprising: a substrate;a dielectric disposed on the substrate, the dielectric including TaxSiyOzNr (x, y, z, r>0) structured as an arrangement of one or more monolayers, wherein the dielectric is structured as a tunnel gate insulator in a vertical floating gate transistor and the dielectric is further structured as a nanolaminate comprising alternative layers of tantalum nitride and tantalum silicon oxynitride; anda metal on and contacting the dielectric. 2. The electronic device of claim 1, wherein the dielectric consists essentially of the TaxSiyOzNr. 3. The electronic device of claim 1, wherein the electronic device includes contacts to couple the electronic device to other apparatus of a system. 4. The electronic device of claim 1, wherein the metal includes one or more of aluminum, tungsten, molybdenum, gold, silver, a gold alloy, a silver alloy, copper, platinum, rhenium, ruthenium, rhodium, nickel, osmium, palladium, iridium, cobalt, germanium, WN, TiN, TaN, or a metal nitride other than WN, TiN, and TaN. 5. The electronic device of claim 1, wherein the tantalum silicon oxynitride is structured as a film doped with elements or compounds other than silicon, tantalum, oxygen, and nitrogen. 6. The electronic device of claim 1, wherein the dielectric includes one or more of SiaOb, SicNd, TacOf, TagNh, SikOlNm, or TanOpNq (a, b, c, d, e, f, g, h, k, l, m, n, p, and q>0) in addition to the TaxSiyOzNr. 7. The electronic device of claim 1, wherein the dielectric includes one or more of an insulating metal oxide, an insulating nitride, an insulating oxynitride, or an insulating silicate. 8. The electronic device of claim 1, wherein the dielectric is further structured as a capacitor dielectric in a capacitor. 9. A wafer comprising: a repeated pattern of dice on a substrate, each die having an electronic device, the electronic die including a dielectric disposed on the substrate, the dielectric including TaxSiyOzNr (x, y, z, r>0) structured as an arrangement of one or more monolayers, wherein the dielectric is structured as a tunnel gate insulator in a vertical floating gate transistor and the dielectric is further structured as a nanolaminate comprising alternating layers of tantalum oxynitride and tantalum silicon oxynitride; anda metal on and contacting the dielectric. 10. The wafer of claim 9, wherein the substrate includes a silicon substrate, a silicon germanium substrate, a germanium substrate, a gallium arsenide substrate, or as silicon-on-sapphire substrate. 11. The wafer of claim 9, wherein the electronic device includes a memory array. 12. An electronic apparatus comprising: an array of memory cells on a substrate, each memory cell including a dielectric having TaxSiyOzNr (x, y, z, r>0) structured as an arrangement of one or more monolayers, wherein the dielectric is structured as a tunnel gate insulator in a vertical floating gate transistor and the dielectric is further structured as a nanolaminate comprising alternating layers of silicon oxynitride and tantalum silicon oxynitride; anda metal on and contacting the dielectric. 13. The electronic apparatus of claim 12, wherein the dielectric and the metal are further structured as a capacitor in each memory cell. 14. The electronic apparatus of claim 12, wherein the dielectric and the metal are structured in a floating gate transistor in each memory cell. 15. The electronic apparatus of claim 12, wherein the dielectric is structured as the nanolaminate to store charge in a flash memory device. 16. The electronic apparatus of claim 15, wherein the nanolaminate has a charge storage layer to store the charge, the charge storage layer including silicon oxide.
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