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Conditional execution with multiple destination stores 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
  • G06F-009/00
  • G06F-009/44
  • G06F-015/00
출원번호 US-0545458 (2006-10-11)
등록번호 US-8521997 (2013-08-27)
발명자 / 주소
  • Wilson, Sophie
출원인 / 주소
  • Broadcom Corporation
대리인 / 주소
    Sterne, Kessler, Goldstein & Fox PLLC
인용정보 피인용 횟수 : 0  인용 특허 : 32

초록

A method for conditionally performing a SIMD operation causing a predetermined number of result objects to be held in a combination of different ones of a plurality of destination stores, the method comprising receiving and decoding instruction fields to determine at least one source store, a plural

대표청구항

1. A method comprising: receiving, from an instruction stream, a first extended SIMD instruction portion by a first SIMD execution channel, the first extended SIMD instruction portion comprising at least one source store, a plurality of destination stores, an immediate value, and at least one contro

이 특허에 인용된 특허 (32)

  1. Radigan James J. (Sunnyvale CA) Schwartz David A. (Moorpark CA), Activity masking with mask context of SIMD processors.
  2. Li Hungwen (Pleasantville NY) Wang Ching-Chy (Fishkill NY), Adaptive instruction processing by array processor having processor identification and data dependent status registers i.
  3. Baldwin David R. (Weybridge GBX) Wilson Malcolm E. (Salwayash GBX) Trevett Neil F. (Kingston-upon-Thames GBX), Architectures for serial or parallel loading of writable control store.
  4. Artz Ray E. (Apple Valley MN) Martin Richard J. (Eagan MN) Splett Vincent E. (Burnsville MN), Arithmetic computation modifier based upon data dependent operations for SIMD architectures.
  5. Miki Yoshio,JPX ; Shimada Kentaro,JPX ; Hanawa Makoto,JPX, Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition.
  6. Amerson Frederic C. (Santa Clara CA) Gupta Rajiv (Los Altos CA) Kumar Balasubramanian (Cupertino CA) Schlansker Michael S. (Los Altos CA) Worley William S. (Saratoga CA), Computer architecture for reducing delays due to branch instructions.
  7. Branigin Michael H. (151 Ivy Hills Rd. Southbury CT 06488), Computer processor with an efficient means of executing many instructions simultaneously.
  8. Auslander Marc A. (Millwood NY) Cocke John (Bedford NY) Hao Hsieh T. (Chappaqua NY) Markstein Peter W. (Yorktown Heights NY) Radin George (Piermont NY), Condition register architecture for a primitive instruction set machine.
  9. Wilson,Sophie, Conditional execution per lane.
  10. Wilson,Sophie, Conditional execution with multiple destination stores.
  11. Evans Charles W. (Poughkeepsie NY), Control store system with flexible control word selection.
  12. Jonathan H. Shiell ; Patrick W. Bosshart, Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer.
  13. Black Bryan P. (Austin TX) Denman Marvin A. (Austin TX), Data processor with branch target address cache and method of operation.
  14. Benayoun, Alain; Le Pennec, Jean-Francois; Pin, Claude; Michel, Patrick, Hardware device for parallel processing of any instruction within a set of instructions.
  15. Auslander Marc A. (Millwood NY) Cocke John (Bedford NY) Hao Hsieh T. (Chappaqua NY) Markstein Peter W. (Yorktown Heights NY) Radin George (Piermont NY), Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing syste.
  16. Lowe ; Jr. Robert B. (North Chelmsford MA), Method and apparatus for executing an atomic read-modify-write instruction.
  17. Dubey Pradeep Kumar,INX ; Olsson Brett ; Hochsprung Ronald Ray ; Scales ; III Hunter Ledbetter ; Diefendorff Keith Everett, Method and system for a result code for a single-instruction multiple-data predicate compare operation.
  18. Yamada Akira,JPX ; Yoshida Toyohiko,JPX ; Kengaku Toru,JPX, Microprocessor capable of executing condition execution instructions using encoded condition execution field in the inst.
  19. Hoyle, David, Microprocessor with instruction for saturating and packing data.
  20. Hoyle, David; Scales, Richard H.; Wang, Min; Zbiciak, Joseph R., Microprocessor with instructions for shifting data responsive to a signed count value.
  21. Webb Charles F. (Poughkeepsie NY), Multiprocessor system with a shared control store accessed with predicted addresses.
  22. Irie, Naohiko; Werner, Tony Lee, Processor architecture and operation for exploiting improved branch control instruction.
  23. Peleg Alexander (Haifa ILX) Yaari Yaakov (Haifa ILX) Mittal Millind (South San Francisco CA) Mennemeier Larry M. (Boulder Creek CA) Eitan Benny (Haifa ILX), Processor performing packed data multiplication.
  24. Chiarulli Donald M. (4724 Newcomb Dr. Baton Rouge LA 70808) Rudd W. G. (Dept. of Computer Science Oregon State University Corvallis OR 97331) Buell Duncan A. (1212 Chippenham Dr. Baton Rouge LA 70808, Processor utilizing reconfigurable process segments to accomodate data word length.
  25. John G. Favor, RISC86 instruction set.
  26. Taylor James L. (Eastleigh GBX), SIMD array processor with global instruction control and reprogrammable instruction decoders.
  27. Okumura Yukihiko,JPX ; Miki Toshio,JPX ; Ohya Tomoyuki,JPX ; Miki Yoshinori,JPX, SIMD multiprocessor with an interconnection network to allow a datapath element to access local memories.
  28. Wilson,Sophie, Setting execution conditions.
  29. Nguyen Le Trong ; Song Seungyoon Peter ; Mohamed Moataz A. ; Park Heonchul ; Wong Roney Sau Don, Single-instruction-multiple-data processing using multiple banks of vector registers.
  30. Thayer John S. ; Favor John G. ; Weber Frederick D., System and method for conditional moving an operand from a source register to destination register.
  31. Kumar Manoj (Yorktown Heights NY) Tsao Michael Mi. (Yorktown Heights NY), System with flexible local control for modifying same instruction partially in different processor of a SIMD computer sy.
  32. Jan Tschunko DE; Friedhelm Soffge DE, Washer element for a wheel bolt and/or wheel nut of a motor vehicle wheel.
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