Electronic device for protecting against a polarity reversal of a DC power supply voltage, and its application to motor vehicles
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02H-003/00
H02H-003/18
출원번호
US-0842766
(2010-07-23)
등록번호
US-8547671
(2013-10-01)
우선권정보
FR-09 55273 (2009-07-28)
발명자
/ 주소
Pavlin, Antoine
출원인 / 주소
STMicroelectronics (Rousset) SAS
대리인 / 주소
Slater & Matsil, L.L.P.
인용정보
피인용 횟수 :
1인용 특허 :
17
초록▼
The electronic device for protecting against a polarity reversal of a DC power supply voltage comprises, produced within one and the same integrated circuit, an N-channel main transistor (TP) mounted on the line of expected positive polarity of the power supply voltage and command means (MCM) for th
The electronic device for protecting against a polarity reversal of a DC power supply voltage comprises, produced within one and the same integrated circuit, an N-channel main transistor (TP) mounted on the line of expected positive polarity of the power supply voltage and command means (MCM) for the main transistor comprising a charging pump circuit (CP), associated with a dynamic biasing circuit (MCTRL) for the substrate regions of active components connected to the main transistor.
대표청구항▼
1. An electronic device comprising: input means having a first input terminal for receiving an expected positive polarity of an input DC power supply voltage;output means having a first output terminal for delivering the positive polarity of an output DC power supply voltage; andprotection means for
1. An electronic device comprising: input means having a first input terminal for receiving an expected positive polarity of an input DC power supply voltage;output means having a first output terminal for delivering the positive polarity of an output DC power supply voltage; andprotection means for protecting against a polarity reversal of the input DC power supply voltage coupled between the input means and the output means, the protection means including the following integrated components: an N-channel main transistor , the source of which is coupled to the first input terminal and the drain of which is coupled to the first output terminal, command means configured to render the main transistor blocked in the event of a polarity reversal and conducting otherwise, and control means configured to dynamically adjust the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor according to the value of the voltages present at the source and the drain of the main transistor and the type of conductivity of the substrate regions. 2. The device according to claim 1, in which the substrate regions of said components are produced within semiconductive regions having a conductivity opposite to that of the substrate regions, the semiconductive regions (RGS) being connected either to the first output terminal (BS1) or to ground depending on the type of conductivity of these semiconductive regions. 3. The device according to claim 2, in which the substrate regions of said components are of P-conductivity type formed in semiconductive regions of N-conductivity type connected to the first output terminal, and the control means are configured to link said P-conductivity type substrate regions to the source of the main transistor if the source voltage is less than the drain voltage or to the drain of the main transistor if the source voltage is greater than the drain voltage. 4. The device according to claim 2, in which the control means comprises a comparator having two inputs respectively connected to the source and to the drain of the main transistor, and a multiplexer having an input connected to said substrate regions, two outputs respectively connected to the source and to the drain of the main transistor, and a command input connected to the output of the comparator. 5. The device according to claim 2, in which the control means comprises a first control transistor having a substrate region connected to its source, the drain of which is connected to the source of the main transistor and the gate of which is connected to the drain of the main transistor, and a second control transistor configured to be conducting, having its source connected to the drain of the main transistor, its substrate region connected to its drain and to the substrate region of the first control transistor and its gate connected to its drain, the drain of this second control transistor being connected to the source of the first control transistor, the substrate regions of said components being connected to the substrate regions of the first and second control transistors which themselves form part of said components. 6. The device according to claim 1, in which the command means comprises a charging pump circuit, the output of which is connected to the gate of the main transistor. 7. The device according to claim 6, in which the command means comprises a voltage regulation circuit connected to the first output terminal and powering the charging pump. 8. The device according to claim 1, produced in N-type technology within a single integrated circuit. 9. The device according to claim 1, wherein the main transistor is a power MOS transistor. 10. An electronic device for protecting against a polarity reversal of a DC power supply voltage, comprising: an N-channel main transistor mounted on a line of expected positive polarity of the DC power supply voltage;the dynamic biasing circuit configured to bias substrate regions of active components connected to the main transistor according to the value of voltages present at the source and at drain of the main transistor and the type of conductivity of the substrate regions; andcommand means for the main transistor comprising a charging pump circuit associated with the dynamic biasing circuit;wherein the main transistor and the command means are formed on a single integrated circuit. 11. A method for protection of an electronic unit against polarity reversals of a DC power supply comprising: receiving an expected positive polarity of an input DC power supply voltage at a first input terminal; delivering the positive polarity of an output DC power supply voltage to the electronic unit at a first output terminal; andprotecting against a polarity reversal of the input DC power supply voltage coupled between the first input terminal and the first output terminal by rendering a main transistor, having its source coupled to the first input terminal and its drain coupled to the first output terminal, blocked in the event of a polarity reversal and conducting otherwise and by dynamically adjusting the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor. 12. A system comprising: a generator of a DC power supply voltage;an electronic unit designed to be powered by a DC voltage; anda device coupled between the generator and the electronic unit, the device including: a first input terminal configured to receive an expected positive polarity of an input DC power supply voltage;a first output terminal configured to deliver the positive polarity of an output DC power supply voltage; andprotection means for protecting against a polarity reversal of the input DC power supply voltage coupled between the first input terminal and the first output terminal, the protection means including the following integrated components: an N-channel main transistor , the source of which is coupled to the first input terminal and the drain of which is coupled to the first output terminal, command means configured to render the main transistor blocked in the event of a polarity reversal and conducting otherwise, and control means configured to dynamically adjust the bias of substrate regions of respective components connected to the main transistor by connecting the substrate regions either to the source or to the drain of the main transistor according to the value of the voltages present at the source and the drain of the main transistor. 13. The system of claim 12 wherein the components of the protection means are formed on a single integrated circuit.
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