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Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/092
출원번호 US-0754384 (2010-04-05)
등록번호 US-8552509 (2013-10-08)
발명자 / 주소
  • Becker, Scott T.
  • Mali, Jim
  • Lambert, Carole
출원인 / 주소
  • Tela Innovations, Inc.
대리인 / 주소
    Martine Penilla Group, LLP
인용정보 피인용 횟수 : 3  인용 특허 : 492

초록

A semiconductor device includes conductive features that are each defined within any one gate level channel uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and firs

대표청구항

1. An integrated circuit, comprising: a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction,

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  201. Kerzman, Joseph Peter; Rezek, James Edward, Method and apparatus for selecting and aligning cells using a placement tool.
  202. Bendik, Joseph J.; Hankinson, Matt, Method and apparatus for the production of process sensitive lithographic features.
  203. Sezginer,Abdurrahman, Method and apparatus of model-based photomask synthesis.
  204. Ludwig, Burkhard; Mueller, Uwe, Method and device for classifying cells in a layout into a same environment and their use for checking the layout of an electronic circuit.
  205. Pileggi,Lawrence T.; Strojwas,Andrzej J.; Lanza,Lucio L., Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features.
  206. Campbell,John E.; Devine,William T.; Srikrishnan,Kris V., Method and structure for buried circuits and devices.
  207. Shenton Graham (Monte Sereno CA) Jones Ioan G. (Los Gatos CA) Lucas David W. (Saratoga CA) Barton Ronald E. (Saratoga CA), Method and structure for use in designing and building electronic systems in integrated circuits.
  208. Andreev,Alexandre; Pavisic,Ivan; Ivanovic,Lav, Method and system for classifying an integrated circuit for optical proximity correction.
  209. Pack,Robert C.; Scheffer,Louis K., Method and system for context-specific mask inspection.
  210. Chang, Keh-Jeng; Chang, Li-Fu; Mathews, Robert G.; Walker, Martin G., Method and system for extraction of parasitic interconnect impedance including inductance.
  211. Ho Wai-Yan ; Tang Hongbo, Method and system for layout verification of an integrated circuit design with reusable subdesigns.
  212. Kamat,Vishnu Govind, Method and system for managing design corrections for optical and process effects based on feature tolerances.
  213. Gupta, Puneet; Kahng, Andrew B.; Park, Chul Hong, Method and system for placing layout objects in a standard-cell layout.
  214. Govil, Pradeep Kumar; Tsacoyeanes, James, Method and system for selective linewidth optimization during a lithographic process.
  215. Bhattacharya,Debashis; Boppana,Vamsi; Roy,Rabindra; Roy,Jayanta, Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks.
  216. Bakarian, Sergei; Segal, Julie, Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design.
  217. Sezginer, Abdurrahman; Yenikaya, Bayram, Method for checking printability of a lithography target.
  218. Crouse, James V.; Lowe, Terry M.; Miao, Limin; Montstream, James R.; Vogl, Norbert; Wyckoff, Colleen A., Method for comprehensively verifying design rule checking runsets.
  219. Kahng,Andrew B.; Gupta,Puneet; Sylvester,Dennis; Yang,Jie, Method for correcting a mask design layout.
  220. Tanaka, Masakazu; Fukui, Masahiro, Method for design of partial circuit.
  221. Ponnapalli Saila (Dutchess County NY) Soyuer Mehmet (Westchester County NY) Ewen John F. (Westchester County NY), Method for designing high-Q inductors in silicon technology without expensive metalization.
  222. Amy A. Winder ; Werner Juengling, Method for designing photolithographic reticle layout, reticle, and photolithographic process.
  223. Winder, Amy A.; Juengling, Werner, Method for designing photolithographic reticle layout, reticle, and photolithographic process.
  224. Kelberlau,Ulrich; Ingram,Peter; Zommer,Nathan, Method for fabricating forward and reverse blocking devices.
  225. Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit having at least three linear-shaped gate electrode level conductive features of equal length positioned side-by-side at equal pitch.
  226. Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch.
  227. Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segment.
  228. Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segment.
  229. Becker, Scott T.; Smayling, Michael C., Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level.
  230. Sandhu,Sukesh; Sandhu,Gurtej S., Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus.
  231. Cui,Yuping; Mansfield,Scott M., Method for improving optical proximity correction.
  232. Hsu Sheng Teng, Method for manufacturing a CMOS self-aligned strapped interconnection.
  233. Bodendorf, Christof Tilmann; Thiele, Jörg, Method for optimizing and method for producing a layout for a mask, preferably for use in semiconductor production, and computer program therefor.
  234. Misaka, Akio; Odanaka, Shinji, Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI.
  235. Misaka,Akio; Odanaka,Shinji, Method for planning layout for LSI pattern, method for forming LSI pattern and method for generating mask data for LSI.
  236. Fujimaga Masato (Hyogo JPX), Method for predicting the three-dimensional topography of surfaces of semiconductor devices after reflow processing.
  237. Semmler,Armin, Method for producing a mask layout avoiding imaging errors for a mask.
  238. Wang,Hsin Shih; Shieh,Shang Jyh; Ku,Ming Hsin, Method for programming a routing layout design through one via layer.
  239. Ramaswamy, S. Ram; Alcorn, Charles N.; Brown, III, Arnett J.; Butts, Tatia E., Method for providing a fill pattern for an integrated circuit design.
  240. Kokubun,Tetsuya, Method for providing layout design and photo mask.
  241. Van Ginneken, Lukas P. P. P.; Groeneveld, Patrick R.; Philipsen, Wilhelmus J. M., Method for storing multiple levels of design data in a common database.
  242. Baba Ali,Nabila, Method for the generation of variable pitch nested lines and/or contact holes using fixed size pixels for direct-write lithographic systems.
  243. Goldbach,Matthias; Hecht,Thomas; L체tzen,J철rn; Sell,Bernhard, Method for the production of a self-adjusted structure on a semiconductor wafer.
  244. Williams,Patrick M.; Cho,Ee K.; Hathaway,David J.; Hsu,Mei Ting; Lange,Lawrence K.; Northrop,Gregory A.; Visweswariah,Chandramouli; Washburn,Cindy ShuiKing; Zhou,Jun, Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices.
  245. DeCamp William Frantz ; Earl Laurice Thorsen ; Minahan Jason Steven ; Montstream James Robert ; Nickel Daniel John ; Oler ; Jr. Joseph James ; Williams Richard Quimby, Method for verifying design rule checking software.
  246. Gupta,Puneet; Heng,Fook Luen; Lavin,Mark A., Method of IC fabrication, IC mask fabrication and program product therefor.
  247. Chao Ying-Chen,TWX ; Chen Chia-Hsiang,TWX ; Sheu Jhy-Sheng,TWX, Method of automatic dummy layout generation.
  248. Fritze, Michael; Tyrrell, Brian, Method of design and fabrication of integrated circuits using regular arrays and gratings.
  249. Watanabe, Susumu, Method of designing integrated circuit and apparatus for designing integrated circuit.
  250. Becker, Scott T.; Smayling, Michael C., Method of fabricating integrated circuit including at least six linear-shaped conductive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length.
  251. Chen J. Fung ; Wampler Kurt E. ; Laidig Tom, Method of fine feature edge tuning with optically-halftoned mask.
  252. Hui, Angela T.; Singh, Bhanwar, Method of forming smaller contact size using a spacer hard mask.
  253. Shi, Xuelong; Chen, Jang Fung; Hsu, Duan-Fu Stephen, Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs.
  254. Tadokoro Hirofumi,JPX ; Arai Kenji,JPX, Method of laying out interconnections.
  255. Zhang,Guohong; O'Brien,Sean, Method of locating sub-resolution assist feature(s).
  256. Rowson James A. (Fremont CA) Trimberger Stephen M. (San Jose CA), Method of making a customized semiconductor integrated device.
  257. Mokhlesi, Nima; Scheuerlein, Roy, Method of making three dimensional NAND memory.
  258. Tamura,Naoyuki; Urakawa,Yukihiro, Method of manufacturing a semiconductor integrated circuit, a program for a computer automated design system, and a semiconductor integrated circuit.
  259. Kobayashi, Kazuhiko; Miyazaki, Kou, Method of manufacturing semiconductor integrated circuit device.
  260. Hashimoto, Naotaka; Hoshino, Yutaka; Ikeda, Shuji, Method of manufacturing semiconductor integrated circuit device having capacitor element.
  261. Yelehanka, Pradeep; Chen, Tong Qing; Han, Zhi Yong; Zheng, Zhen Jia; Ong, Kelvin; Gu, Tian Hao; Cheah, Syn Kean, Method of manufacturing semiconductor local interconnect and contact.
  262. Samuels, Donald J., Method of optical proximity correction with sub-resolution assists.
  263. Charlebois,Steven E.; Dunn,Paul E.; Rohrbaugh, III,George W., Method of optimizing customizable filler cells in an integrated circuit physical design process.
  264. Chun-Chih Yang TW; Yung-Chung Chang TW; Shu-Tzu Wang TW, Method of placement and routing for an array device.
  265. Burstein, Michael; Ginzburg, Boris, Method of placing and routing for power optimization and timing closure.
  266. Reyes Alberto J. ; Snyder Daniel J. ; Chamoun Sleiman N. ; Ramondetta Karen S., Method of selecting device threshold voltages for high speed and low power.
  267. Kotani,Toshiya; Tanaka,Satoshi; Hashimoto,Koji; Inoue,Soichi; Mori,Ichiro, Method of setting process parameter and method of setting process parameter and/or design rule.
  268. Laidig,Thomas; Chen,Jang Fung; Shi,Xuelong; Schlief,Ralph; Hollerbach,Uwe; Wampler,Kurt E., Method of two dimensional feature model calibration and optimization.
  269. Armbrust, Douglas S.; Martin, Dale W.; Rankin, Jed H.; Tousley, Sylvia, Method to define and tailor process limited lithographic features using a modified hard mask process.
  270. Liebmann, Lars W.; Mansfield, Scott; Wong, Alfred K., Method to determine optical proximity correction and assist feature rules which account for variations in mask dimensions.
  271. Chou,Shih Wei; Tsai,Ming Hsing; Lin,Ming Wei, Method to improve planarity of electroplated copper.
  272. Shin,Jaw Jung; Ke,Chih Ming; Lin,Burn Jeng, Method to reduce CD non-uniformity in IC manufacturing.
  273. Kahng, Andrew B.; Park, Chul-Hong, Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction.
  274. Visweswariah,Chandramouli; Xiong,Jinjun; Zolotov,Vladimir, Method, system, and program product for computing a yield gradient from statistical timing.
  275. Chuang, Harry; Chang, Victor C. Y.; Chen, Yung-Shun; Hou, Shang Y., Methodology to characterize metal sheet resistance of copper damascene process.
  276. Rahmat,Khalid; McElvain,Kenneth S., Methods and apparatuses for thermal analysis based circuit design.
  277. Furnish, Geoffrey Mark; LeBrun, Maurice J.; Bose, Subhasis, Methods and systems for placement.
  278. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.
  279. Smayling, Michael C.; Becker, Scott T., Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same.
  280. Reed, Brian; Smayling, Michael C.; Hong, Joseph N.; Fairbanks, Stephen; Becker, Scott T., Methods for defining and utilizing sub-resolution features in linear topology.
  281. Hong, Joseph; Kornachuk, Stephen; Becker, Scott T., Methods for defining contact grid in dynamic array architecture.
  282. Becker, Scott T.; Smayling, Michael C., Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same.
  283. Becker, Scott T.; Smayling, Michael C., Methods for designing semiconductor device with dynamic array section.
  284. Dhrumil Gandhi, Methods for designing standard cell transistor structures.
  285. Rueckes,Thomas; Segal,Brent M., Methods of nanotubes films and articles.
  286. Maziasz Robert L. ; Guruswamy Mohankumar ; Raman Srilata, Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors.
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  288. Capodieci Luigi, Modification of mask layout data to improve writeability of OPC.
  289. Dellinger, Eric, Modular array defined by standard cell logic.
  290. Park,Young Jin; Mueller,Gerhard, Multi-level conductive lines with reduced pitch.
  291. Van Houdt, Jan; Haspeslagh, Luc, Multibit non-volatile memory and method.
  292. Fuchida Yumi,JPX ; Hanari Jun,JPX ; Matsumoto Kazuhiro,JPX ; Kudo Junichi,JPX ; Yoshihara Kunio,JPX ; Takagi Ayako,JPX, Multilayer wiring structure.
  293. Dixit,Abhisek; De Meyer,Kristin, Multiple gate semiconductor device and method for forming same.
  294. Sani, Mehdi Hamidi; Uvieghara, Gregory A., Non-volatile multi-threshold CMOS latch with leakage control.
  295. Sira G. Sudhindranath ; Anand Sethuraman, Off-grid metal layer utilization.
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  298. Zach, Franz Xaver, Optical lithography correction process.
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  300. Yu, Shinn-Sheng, Optical proximity correction common process window maximization over varying feature pitch.
  301. Garza Mario ; Jensen John V. ; Eib Nicholas K. ; Chao Keith K., Optical proximity correction method and apparatus.
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  306. Cadouri, Eitan, Optimization of die placement on wafers.
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  309. Becker, Scott T., Oversized contacts and vias in semiconductor chip defined by linearly constrained topology.
  310. Beahm Martin Emery ; Chappell Terry Ivan ; Joshi Rajiv Vasant, Parameterized cells for generating dense layouts of VLSI circuits.
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  317. Hung,Yung Long; Wu,Yuan Hsun, Phase-shifting mask for equal line/space dense line patterns.
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  319. Rittman, Danny; Oren, Micha, Photomask for reducing power supply voltage fluctuations in an integrated circuit and integrated circuit manufactured with the same.
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  322. Dasasathyan, Srinivasan; Stenz, Guenter; Nag, Sudip K., Placement of clock objects under constraints.
  323. Gordon,Ronald L.; Graur,Ioana C.; Liebmann,Lars W., Pliant SRAF for improved performance and manufacturability.
  324. Kapur Rajiv, Poly routing for chip interconnects with minimal impact on chip performance.
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  327. Groover ; III Robert (Dallas TX) Haken Roger A. (Richardson TX) Holloway Thomas C. (Dallas TX), Process for making integrated circuits having titanium nitride triple interconnect.
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  332. Pileggi, Larry; Schmit, Herman, Programmable gate array based on configurable metal interconnect vias.
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  337. Jacques,Etienne; Kronmiller,Tom, Removal of acute angles in a design layout.
  338. Zhou, Wen Zhan; Yu, Jin; See, Kai Hung Alex, Reticle and optical proximity correction method.
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  363. Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level.
  364. Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment.
  365. Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level.
  366. Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level.
  367. Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions.
  368. Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments.
  369. Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers.
  370. Becker, Scott T.; Smayling, Michael C., Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions.
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  375. Shibayama, Akinori, Semiconductor device and semiconductor memory device.
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  378. Scott M. Mansfield ; Lars W. Liebmann ; Shahid Butt ; Henning Haffner, Semiconductor device fabrication using a photomask with assist features.
  379. Becker, Scott T.; Smayling, Michael C., Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment.
  380. Kanamoto, Toshiki; Ajioka, Yoshihide; Shimazu, Yukihiko; Hamada, Hideyuki, Semiconductor device having a library of standard cells and method of designing the same.
  381. Becker, Scott T.; Smayling, Michael C., Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground.
  382. Becker, Scott T.; Smayling, Michael C., Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch.
  383. Or-Bach, Zvi; Cooke, Laurance, Semiconductor device having borderless logic array and flexible I/O.
  384. Shibutani, Koji, Semiconductor device having cell-based basic element aggregate having protruding part in active region.
  385. Becker, Scott T.; Smayling, Michael C., Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths.
  386. Ryoo,Man Hyoung; Yeo,Gi Sung; Lee,Si Hyeung; Kim,Gyu Chul; Jung,Sung Gon; Park,Chang Min; Cho,Hoo Sung, Semiconductor device having sufficient process margin and method of forming same.
  387. Becker, Scott T.; Smayling, Michael C., Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch.
  388. Becker, Scott T.; Smayling, Michael C., Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances.
  389. Becker, Scott T.; Smayling, Michael C., Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact.
  390. Becker, Scott T.; Smayling, Michael C., Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends.
  391. Inaba, Satoshi, Semiconductor device including n-type and p-type FinFET's constituting an inverter structure.
  392. Becker, Scott T.; Smayling, Michael C., Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size.
  393. Becker, Scott T.; Smayling, Michael C., Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length.
  394. Suzuki, Fumiaki, Semiconductor device with NMOS transistors arranged continuously.
  395. Becker, Scott T.; Smayling, Michael C., Semiconductor device with dynamic array section.
  396. Becker, Scott T.; Smayling, Michael C., Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos.
  397. Houston, Theodore W.; Joyner, Keith A., Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device.
  398. Becker, Scott T.; Smayling, Michael C., Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region.
  399. Becker, Scott T.; Smayling, Michael C., Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region.
  400. Becker, Scott T.; Smayling, Michael C., Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction.
  401. Sakemi Kazuhiro,JPX ; Kikuda Shigeru,JPX ; Kawasaki Satoshi,JPX, Semiconductor device with improved noise resistivity.
  402. Becker, Scott T.; Smayling, Michael C., Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion region.
  403. Becker, Scott T.; Smayling, Michael C., Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length.
  404. Becker, Scott T.; Smayling, Michael C., Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts.
  405. Kinoshita,Koichi, Semiconductor integrated circuit.
  406. Takayama, Kazuhisa, Semiconductor integrated circuit and semiconductor integrated circuit wiring layout method.
  407. Kinoshita, Eita; Mizuno, Makoto, Semiconductor integrated circuit basic cell semiconductor integrated circuit using the same.
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이 특허를 인용한 특허 (3)

  1. Qian, Qi-De, Integrated circuits having in-situ constraints.
  2. Blatchford, James Walter; Aton, Thomas J., Layout method to minimize context effects and die area.
  3. Blatchford, James Walter; Aton, Thomas J., Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two.
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