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Interconnect structure containing various capping materials for electrical fuse and other related applications 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0537879 (2012-06-29)
등록번호 US-8558384 (2013-10-15)
발명자 / 주소
  • Hsu, Louis L.
  • Tonti, William R.
  • Yang, Chih-Chao
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Canale, Anthony
인용정보 피인용 횟수 : 2  인용 특허 : 51

초록

A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first st

대표청구항

1. A structure comprising: a first macro having a metal wiring layer on a first level electrically connected through an opening in a first capping layer to a metal wiring layer on a second layer and a second capping layer over the metal wiring layer on the second layer which has a first electromigra

이 특허에 인용된 특허 (51)

  1. Yang, Chih-Chao; Clevenger, Lawrence A.; Dalton, Timothy J.; Fuller, Nicholas C.; Hsu, Louis C., Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application.
  2. Yang,Chih Chao; Clevenger,Lawrence A.; Dalton,Timothy J.; Fuller,Nicholas C.; Hsu,Louis C., Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application.
  3. Anderson,Brent A.; Bryant,Andres; Gambino,Jeffrey P.; Stamper,Anthony K., Air-gap insulated interconnections.
  4. Dubin, Valery M.; Moon, Peter K., Apparatus for an improved air gap interconnect structure.
  5. Adkisson, James W.; Gambino, Jeffrey P.; Jaffe, Mark D.; Rassel, Richard J., Bond pad for wafer and package for CMOS imager.
  6. Saenger,Katherine L; Surendra,Maheswaran; Karecki, legal representative,Anna Dorothy; Nitta,Satya V; Purushothaman,Sampath; Colburn,Matthew E; Dalton,Timothy J; Huang,Elbert; Karecki,Simon M, Closed air gap interconnect structure.
  7. Huang, Liu; Sudijono, John; Wee, Koh Yee, Composite barrier/etch stop layer comprising oxygen doped SiC and SiC for interconnect structures.
  8. Sudijono, John; Hsia, Liang Ch O; Ping, Liu Wu, Copper recess formation using chemical process for fabricating barrier cap for lines and vias.
  9. Naem, Abdalla Aly, Copper-compatible fuse target.
  10. Ngo, Minh Van; Besser, Paul Raymond; Zhao, Larry, Cu capping layer deposition with improved integrated circuit reliability.
  11. Hsu, Louis Lu-Chen; Mandelman, Jack Allan; Tonti, William Robert; Yang, Chih-Chao, Electronic fuses in semiconductor integrated circuits.
  12. Wang, Ping-Chuan; Li, Wai-Kin, Empty vias for electromigration during electronic-fuse re-programming.
  13. Barth, Hans-Joachim; Felsner, Petra; Kaltalioglu, Erdem; Friese, Gerald, FBEOL process for Cu metallizations free from Al-wirebond pads.
  14. Yu, Ta-Lee, Fabricating an electrical metal fuse.
  15. Sakoh,Takashi, Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance.
  16. Ngo Minh Van ; Cheung Robin W., High density capping layers with improved adhesion to copper interconnects.
  17. Yang,Chih Chao, High-density 3-dimensional resistors.
  18. Yang, Chih-Chao; Wang, Ping-Chuan; Wang, Yun-Yu, Interconnect structure having enhanced electromigration reliability and a method of fabricating same.
  19. Yang,Chih Chao; Hsu,Louis L.; Wong,Keith Kwong Hon; Dalton,Timothy Joseph; Radens,Carl; Clevenger,Larry, Interconnect structures and methods of making thereof.
  20. Oda Noriaki,JPX, Method for fabricating multilevel interconnection structure for semiconductor devices.
  21. van Ngo, Minh, Method for forming nitride capped Cu lines with reduced hillock formation.
  22. Oh,Hyeok sang; Chung,Ju hyuck; Kim,Il goo, Method of fabricating dual damascene interconnection.
  23. Lee,Kyoung woo; Lee,Soo geun; Park,Wan jae; Kim,Jae hak; Shin,Hong jae, Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler.
  24. Wong,Lawrence D.; Leu,Jihperng; Kloster,Grant; Ott,Andrew; Morrow,Patrick, Method of making semiconductor device using a novel interconnect cladding layer.
  25. Leu, Jihperng; Thomas, Christopher D., Method of making semiconductor device using an interconnect.
  26. Chen,Bo Wei; Wang,Hsien Shou; Hsu,Shih Ping, Method to manufacture a coreless packaging substrate.
  27. Takewaki, Toshiyuki; Kunishima, Hiroyuki, Narrow and wide copper interconnections composed of (111), (200) and (511) surfaces.
  28. Wang, Ming-Tsong; Ong, Tong-Chern, One-time-programmable anti-fuse formed using damascene process.
  29. Tzeng Wen-Tsing,TWX ; Yang Chun-Pin,TWX ; Lin Hsing-Lien,TWX, Passivation layer etching process for memory arrays with fusible links.
  30. Yang,Chao Hsiang, Protective metal structure and method to protect low-K dielectric layer during fuse blow process.
  31. Chao-Kun Hu ; Robert Rosenberg ; Judith Marie Rubino ; Carlos Juan Sambucetti ; Anthony Kendall Stamper, Reduced electromigration and stressed induced migration of Cu wires by surface coating.
  32. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  33. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD.
  34. Yang, Chih-Chao; Van Der Straten, Oscar, Reliable via contact interconnect structure.
  35. Burr, Geoffrey W.; Kothandaraman, Chandrasekharan; Lam, Chung Hon; Liu, Xiao Hu; Rossnagel, Stephen M.; Tyberg, Christy S.; Wisnieff, Robert L., Reprogrammable fuse structure and method.
  36. Burke, Peter A.; Hose, Sallie; Shastri, Sudhama C., Semiconductor component and method of manufacture.
  37. Noguchi,Junji; Matsumoto,Takashi; Oshima,Takayuki; Onozuka,Toshihiko, Semiconductor device and manufacturing method of the same.
  38. Ueda, Takehiro, Semiconductor device and method for cutting electric fuse.
  39. Takeda,Kenichi; Ryuzaki,Daisuke; Hinode,Kenji; Mine,Toshiyuki, Semiconductor device and method manufacturing the same.
  40. Watanabe, Kenichi, Semiconductor device having capacitor capable of reducing additional processes and its manufacture method.
  41. Park, Seung Han; Lee, Ki Young, Semiconductor device having fuse and capacitor at the same level and method of fabricating the same.
  42. Park,Seung Han; Lee,Ki Young, Semiconductor device having fuse and capacitor at the same level and method of fabricating the same.
  43. Harada,Takeshi, Semiconductor device having via connecting between interconnects.
  44. Hotta, Katsuhiko; Sasahara, Kyoko; Hayamizu, Taichi; Kawano, Yuichi, Semiconductor device with fuse and a method of manufacturing the same.
  45. Makoto Kotou JP; Shinya Iwasa JP, Semiconductor memory device manufacturing method with fuse cutting performance improved.
  46. Yang, Chih Chao; Edelstein, Daniel C.; Mandelman, Jack A.; Hsu, Louis L., Semiconductor structure for fuse and anti-fuse applications.
  47. Yang, Chih-Chao; Hsu, Louis C.; Joshi, Rajiv V., Simultaneous grain modulation for BEOL applications.
  48. Hsu, Louis L.; Tonti, William R.; Yang, Chih-Chao, Structure for interconnect structure containing various capping materials for electrical fuse and other related applications.
  49. Bernstein, Kerry; Dalton, Timothy J.; Gambino, Jeffrey P.; Jaffe, Mark D.; Luce, Stephen E.; Stamper, Anthony K., Three dimensional vertical E-fuse structures and methods of manufacturing the same.
  50. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
  51. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.

이 특허를 인용한 특허 (2)

  1. Barwicz, Tymon; Bruce, Robert L.; Kamlapurkar, Swetha, Far back end of the line stack encapsulation.
  2. Bonilla, Griselda; Bao, Junjing; Choi, Samuel S.; Filippi, Ronald G.; Lustig, Naftali E.; Simon, Andrew H., Method to resolve hollow metal defects in interconnects.
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