IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0742430
(2008-11-11)
|
등록번호 |
US-8563903
(2013-10-22)
|
우선권정보 |
KR-10-2007-0114962 (2007-11-12); KR-10-2008-0042489 (2008-05-07); KR-10-2008-0052257 (2008-06-03) |
국제출원번호 |
PCT/KR2008/006630
(2008-11-11)
|
§371/§102 date |
20101001
(20101001)
|
국제공개번호 |
WO2009/064098
(2009-05-22)
|
발명자
/ 주소 |
- Kim, Hyun-Tak
- Lee, Yong-Wook
- Kim, Bong-Jun
- Yun, Sun-Jin
|
출원인 / 주소 |
- Electronics and Telecommunications Research Institute
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
3 |
초록
▼
Provided are a method and circuit for controlling heat generation of a power transistor, in which the power transistor can be protected by preventing heat generation of the power transistor by using a metal-insulator transition (MIT) device that can function as a fuse and can be semi-permanently use
Provided are a method and circuit for controlling heat generation of a power transistor, in which the power transistor can be protected by preventing heat generation of the power transistor by using a metal-insulator transition (MIT) device that can function as a fuse and can be semi-permanently used. The circuit for controlling heat generation of a transistor includes a metal-insulator transition (MIT) device in which abrupt MIT occurs at a predetermined critical temperature; and a power transistor connected to a driving device and controlling power-supply to the driving device, wherein the MIT device is attached to a surface or heating portion of the transistor and is connected to a base terminal or gate terminal of the transistor or a surrounding circuit from a circuit point of view, and wherein when a temperature of the transistor increases to a temperature equal to or greater than the predetermined critical temperature, the MIT device reduces or shuts off a current of the transistor so as to prevent heat generation of the transistor.
대표청구항
▼
1. A circuit for controlling heat generation of a transistor, the circuit comprising: a metal-insulator transition (MIT) device in which abrupt MIT occurs at a predetermined critical temperature; anda power transistor connected to a driving device and controlling power-supply to the driving device,w
1. A circuit for controlling heat generation of a transistor, the circuit comprising: a metal-insulator transition (MIT) device in which abrupt MIT occurs at a predetermined critical temperature; anda power transistor connected to a driving device and controlling power-supply to the driving device,wherein the MIT device is attached to a heating surface or heating portion of the transistor and is connected to a base terminal or gate terminal of the transistor or a surrounding circuit from a circuit point of view,wherein when a temperature of the transistor increases to a temperature equal to or greater than the predetermined critical temperature, the MIT device reduces or shuts off a current of the transistor so as to prevent heat generation,wherein the MIT device comprises an MIT thin film where abrupt MIT occurs at the critical temperature, and at least two electrode thin films in contact with the MIT thin film,wherein the MIT device is a stack type in which the at least two electrode thin films are disposed between the MIT thin film, or a horizontal type in which the at least two electrode thin films disposed at both sides of the MIT thin film, andwherein the MIT device is packaged in a dual in-line package (DIP) type in which the MIT thin film and the at least two electrode thin films are sealed by a sealing member, or is packaged in a CAN type in which a predetermined portion of the MIT thin film is exposed. 2. The circuit for controlling heat generation of a transistor of claim 1, wherein the translator is an NPN or PNP junction transistor. 3. The circuit for controlling heat generation of a transistor of claim 1, wherein the translator is a metal oxide semiconductor (MOS) transistor. 4. The circuit for controlling heat generation of a transistor of claim 1, wherein the translator comprises any one of a photo diode (or photo transistor), photo relay and photo silicon controlled rectifier (SCR) using light input to the base terminal. 5. The circuit for controlling heat generation of a transistor of claim 1, wherein the transistor comprises any one of an insulated gate bipolar transistor (IGBT), an SCR and a triac. 6. The circuit for controlling heat generation of a transistor of claim 1, wherein the MIT device is a DIP type MIT device, wherein the DIP type MIT device comprises two external electrodes connected to the at least two electrode thin films and an external heating terminal detecting heat generation of the driving device and connected to the MIT thin film. 7. The circuit for controlling heat generation of a transistor of claim 1, wherein the MIT device is a CAN type MIT device, wherein the CAN type MIT device includes two external electrode terminals connected to the at least two electrode thin films and detects heat generation of the driving device through infrared rays input through the predetermined portion that is exposed. 8. The circuit for controlling heat generation of a transistor of claim 1, wherein the MIT device is manufactured of a thin film, ceramic or a single crystal. 9. The circuit for controlling heat generation of a transistor of claim 1, wherein the MIT device is formed of VO2. 10. The circuit for controlling heat generation of a transistor of claim 1, wherein the MIT device and the transistor are designed as a single chip. 11. The circuit for controlling heat generation of a transistor of claim 10, wherein the single chip has a structure in which the MIT device is disposed on the transistor. 12. The circuit for controlling heat generation of a transistor of claim 11, wherein the MIT device is disposed on an insulating layer formed on the transistor, wherein an electrode of the MIT device and an electrode of the transistor are connected to each other via a contact hole formed in the insulating layer. 13. The circuit for controlling heat generation of a transistor of claim 1, wherein the MIT device and the transistor are integrated and used in a single package. 14. The circuit for controlling heat generation of a transistor of claim 1, wherein the critical temperature varies according to a voltage applied to the MIT device. 15. An electric-electronic circuit system comprising the circuit for controlling heat generation of a transistor of claim 1. 16. The electric-electronic circuit system of claim 15, further comprising a cellular phone, a computer, a cell charger, a motor controller, a power amplifier including audio equipment, a power controlling circuit and power supply of an electric-electronic device and an inner circuit of a integrated functional integrated circuit (IC) including a microprocessor. 17. A circuit for controlling heat generation of a transistor, the circuit comprising: an MIT device in which abrupt MIT occurs at a predetermined critical temperature; andtwo power transistors connected to both sides of a driving device and controlling power-supply to the driving device,wherein the MIT device is attached to a heating surface or heating portion of at least one of the two power transistors and is connected to a base terminal or gate terminal of each of the two power transistors from a circuit point of view, andwherein when a temperature of a first transistor of the two power transistors increases to a temperature equal to or greater than the predetermined critical temperature, the MIT device shuts off a current of the first transistor and allows a current to flow through a second transistor of the two power transistors so as to prevent heat generation of the two power transistors. 18. The circuit for controlling heat generation of a transistor of claim 17, wherein one of the two power transistor is an NPN junction transistor and the other of the two power transistors is a PNP junction transistor. 19. The circuit for controlling heat generation of a transistor of claim 17, wherein one of the two power transistors is an N-type MOS transistor and the other of the two power transistors is a P-type MOs transistor, wherein the N-type and P-type MOS transistors are separately formed or integrated as a complementary metal oxide semiconductor (CMOS) transistor. 20. The circuit for controlling heat generation of a transistor of claim 17, wherein the MIT device comprises an MIT thin film where abrupt MIT occurs at the predetermined critical temperature and at least two electrode thin films in contact with the MIT thin film, and wherein the MIT device is a stack type in which the at least two electrode thin films are vertically staked at both sides of the MIT thin film, or a horizontal type in which the at least two electrode thin films are disposed at both ends of the MIT thin film. 21. The circuit for controlling heat generation of a transistor of claim 20, wherein the MIT device is packaged in a dual in-line package (DIP) type in which the MIT thin film and the at least two electrode thin films are sealed by a sealing member, or is packaged in a CAN type in which a predetermined portion of the MIT thin film is exposed. 22. The circuit for controlling heat generation of a transistor of claim 17, wherein the MIT device is manufactured of a thin film, ceramic or a single crystal. 23. The circuit for controlling heat generation of a transistor of claim 17, wherein the MIT device is formed of VO2. 24. The circuit for controlling heat generation of a transistor of claim 17, wherein the MIT device and the transistor are designed as a single chip. 25. The circuit for controlling heat generation of a transistor of claim 24, wherein the single chip has a structure in which the MIT device is disposed on any one of the two power transistors. 26. The circuit for controlling heat generation of a transistor of claim 24, wherein the single chip has a structure in which the MIT device is commonly disposed on the two power transistors. 27. The circuit for controlling heat generation of a transistor of claim 17, wherein the MIT device and the two power transistors are integrated and used in a single package. 28. The circuit for controlling heat generation of a transistor of claim 27, wherein each of the two transistors comprises any one of a photo diode, photo transistor, photo relay or photo silicon controlled rectifier (SCR) using light input to the base terminal. 29. A circuit for controlling heat generation of a transistor, the circuit comprising: an MIT device in which abrupt MIT occurs at a predetermined critical temperature;two power transistors connected to both sides of a driving device and controlling power-supply to the driving device; anda transistor for protecting the MIT device, controlling a current of the MIT device and supplying power towards the driving device,wherein the MIT device is attached to a heating surface or heating portion of at least one of the two power transistors and is connected to a base terminal or gate terminal of each of the two power transistors from a circuit point of view, andwherein when a temperature of the two transistors increases to a temperature equal to or greater than the predetermined critical temperature, the MIT device controls a current supplied to the two transistors so as to control heat generation of the two transistors. 30. The circuit for controlling heat generation of a transistor of claim 29, wherein one of the two power transistor is an NPN junction transistor and the other of the two power transistors is a PNP junction transistor. 31. The circuit for controlling heat generation of a transistor of claim 30, wherein when a temperature of a first transistor of the two transistors increases to a temperature equal to or greater than the critical temperature, the MIT device shuts or reduces a current of the first transistor and allows a current to flow through a second transistor of the two power transistor so as to prevent heat generation of the two power transistors. 32. The circuit for controlling heat generation of a transistor of claim 31, wherein when the second transistor operates so as to repeatedly turn the driving device on/off, another transistor controlling the second transistor is attached to a base of the second transistor. 33. A circuit for controlling heat generation of a transistor, the circuit comprising: a power transistor connected to a driving device and controlling power-supply to the driving device;a first MIT device connected to a base terminal or gate terminal of the transistor or a surrounding circuit, where abrupt MIT occurs at a predetermined critical temperature;a second MIT device connected between a collector terminal and emitter terminal of the transistor, or between a source terminal and drain terminal of the transistor,wherein abrupt MIT occurs at the critical temperature, wherein the first and second MIT devices are attached to a heating surface or heating portions of the transistor, wherein when a temperature of the transistor increases to the critical temperature, the first and second devices operate so as to control a current supplied to the transistor and prevent heat generation of the transistor. 34. The circuit for controlling heat generation of a transistor of claim 33, wherein a transistor protecting any one of the MIT devices is attached thereto.
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