최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0754061 (2010-04-05) |
등록번호 | US-8564071 (2013-10-22) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 1 인용 특허 : 492 |
A semiconductor device includes a substrate having a plurality of diffusion regions defined therein to form first and second p-type diffusion regions, and first and second n-type diffusion regions, with each of these diffusion regions electrically connected to a common node. The first p-type active
A semiconductor device includes a substrate having a plurality of diffusion regions defined therein to form first and second p-type diffusion regions, and first and second n-type diffusion regions, with each of these diffusion regions electrically connected to a common node. The first p-type active area and the second p-type active area are contiguously formed together. The first n-type active area and the second n-type active area are contiguously formed together. Gate electrodes are formed from conductive features that are each defined within any one gate level channel. Each gate level channel is uniquely associated with and defined along one of a number of parallel oriented gate electrode tracks. A first PMOS transistor gate electrode is electrically connected to a second NMOS transistor gate electrode, and a second PMOS transistor gate electrode is electrically connected to a first NMOS transistor gate electrode.
1. An integrated circuit, comprising: a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherei
1. An integrated circuit, comprising: a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction,wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction, andwherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node;a first gate contact defined to physically contact the first gate level feature;a second gate contact defined to physically contact the second gate level feature, wherein the second gate level feature has an extension distance extending away from the second gate contact in the first direction away from the gate electrode of the second transistor of the first transistor type;a third gate contact defined to physically contact the third gate level feature, wherein the third gate level feature has an extension distance extending away from the third gate contact in the first direction away from the gate electrode of the second transistor of the second transistor type;a fourth gate contact defined to physically contact the fourth gate level feature, wherein the fourth gate level feature has an extension distance extending away from the fourth gate contact in the first direction away from the gate electrode of the third transistor of the first transistor type;a fifth gate contact defined to physically contact the fifth gate level feature, wherein the fifth gate level feature has an extension distance extending away from the fifth gate contact in the first direction away from the gate electrode of the third transistor of the second transistor type; anda sixth gate contact defined to physically contact the sixth gate level feature,wherein at least two of the extension distances of the second, third, fourth, and fifth gate level features are different. 2. An integrated circuit as recited in claim 1, wherein the gate electrodes of the first, second, third, and fourth transistors of the first transistor type are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two of the gate electrodes of the first, second, third, and fourth transistors of the first transistor type is substantially equal to an integer multiple of the gate pitch, and wherein the gate electrodes of the first, second, third, and fourth transistors of the second transistor type are positioned according to the gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two of the gate electrodes of the first, second, third, and fourth transistors of the second transistor type is substantially equal to an integer multiple of the gate pitch. 3. An integrated circuit as recited in claim 2, wherein the gate electrode level region includes a seventh gate level feature that forms a gate electrode of a fifth transistor of the first transistor type and a gate electrode of a fifth transistor of the second transistor type. 4. An integrated circuit as recited in claim 3, wherein all gate level features within the gate electrode level region are linear shaped and extend lengthwise in the first direction. 5. An integrated circuit as recited in claim 4, wherein the gate electrode level region includes an eighth gate level feature that does not form a gate electrode of a transistor, the eighth gate level feature positioned such that a distance as measured in the second direction between a first-direction-oriented centerline of the eighth gate level feature and a first-direction-oriented centerline of a gate electrode of a transistor within the gate electrode level region is substantially equal to an integer multiple of the gate pitch. 6. An integrated circuit as recited in claim 1, wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, and wherein at least four of the first, second, third, fourth, fifth, and sixth gate contacts are respectively positioned over the inner portion of the gate electrode level region. 7. An integrated circuit as recited in claim 6, wherein two of the second, third, fourth, and fifth gate level features has a different length as measured in the first direction. 8. An integrated circuit as recited in claim 7, wherein all gate electrodes within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch. 9. An integrated circuit as recited in claim 8, wherein each gate level feature within the gate electrode level region is linear-shaped. 10. An integrated circuit as recited in claim 9, further comprising: an interconnect level region formed above the gate electrode level region, wherein the third gate level feature is electrically connected to the fourth gate level feature through an electrical connection that extends through the interconnect level region. 11. An integrated circuit as recited in claim 6, wherein each of the first, second, third, fourth, fifth, and sixth gate contacts is positioned over the inner portion of the gate electrode level region. 12. An integrated circuit as recited in claim 11, wherein two of the second, third, fourth, and fifth gate level features has a different length as measured in the first direction. 13. An integrated circuit as recited in claim 12, wherein all gate electrodes within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch. 14. An integrated circuit as recited in claim 13, wherein each gate level feature within the gate electrode level region is linear-shaped. 15. An integrated circuit as recited in claim 14, wherein the gate electrode level region includes a seventh gate level feature that forms a gate electrode of a fifth transistor of the first transistor type and a gate electrode of a fifth transistor of the second transistor type. 16. An integrated circuit as recited in claim 15, wherein the second and third transistors of the first transistor type share a first diffusion region of a first diffusion type, wherein the second and third transistors of the second transistor type share a first diffusion region of a second diffusion type, andwherein the first diffusion region of the first diffusion type is electrically connected to the first diffusion region of the second diffusion type. 17. An integrated circuit as recited in claim 1, wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, and wherein either the first or second end of the second gate level feature is an inner end of the second gate level feature positioned over the inner portion of the gate electrode level region, andwherein either the first or second end of the fourth gate level feature is an inner end of the fourth gate level feature positioned over the inner portion of the gate electrode level region, andwherein each of the inner ends of the second and fourth gate level features is substantially aligned to a first position in the first direction. 18. An integrated circuit as recited in claim 17, wherein either the first or second end of the third gate level feature is an inner end of the third gate level feature positioned over the inner portion of the gate electrode level region, and wherein either the first or second end of the fifth gate level feature is an inner end of the fifth gate level feature positioned over the inner portion of the gate electrode level region, andwherein each of the inner ends of the third and fifth gate level features is substantially aligned to a second position in the first direction. 19. An integrated circuit as recited in claim 18, wherein all gate electrodes within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch. 20. An integrated circuit as recited in claim 19, wherein each gate level feature within the gate electrode level region is linear-shaped. 21. An integrated circuit as recited in claim 20, wherein the gate electrode level region includes a seventh gate level feature that does not form a gate electrode of a transistor. 22. An integrated circuit as recited in claim 21, wherein the second and third transistors of the first transistor type share a first diffusion region of a first diffusion type, wherein the second and third transistors of the second transistor type share a first diffusion region of a second diffusion type, andwherein the first diffusion region of the first diffusion type is electrically connected to the first diffusion region of the second diffusion type. 23. A method for creating a layout of an integrated circuit, comprising: operating a computer to define a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction,wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction, andwherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node;operating a computer to define a first gate contact defined to physically contact the first gate level feature;operating a computer to define a second gate contact defined to physically contact the second gate level feature, wherein the second gate level feature has an extension distance extending away from the second gate contact in the first direction away from the gate electrode of the second transistor of the first transistor type;operating a computer to define a third gate contact defined to physically contact the third gate level feature, wherein the third gate level feature has an extension distance extending away from the third gate contact in the first direction away from the gate electrode of the second transistor of the second transistor type;operating a computer to define a fourth gate contact defined to physically contact the fourth gate level feature, wherein the fourth gate level feature has an extension distance extending away from the fourth gate contact in the first direction away from the gate electrode of the third transistor of the first transistor type;operating a computer to define a fifth gate contact defined to physically contact the fifth gate level feature, wherein the fifth gate level feature has an extension distance extending away from the fifth gate contact in the first direction away from the gate electrode of the third transistor of the second transistor type; andoperating a computer to define a sixth gate contact defined to physically contact the sixth gate level feature,wherein at least two of the extension distances of the second, third, fourth, and gate level features are different. 24. A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising: program instructions for defining a gate electrode level region having a number of adjacently positioned gate electrode feature channels, each gate electrode feature channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type,wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type,wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type,wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type,wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction,wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction, andwherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node;program instructions for defining a first gate contact defined to physically contact the first gate level feature;program instructions for defining a second gate contact defined to physically contact the second gate level feature, wherein the second gate level feature has an extension distance extending away from the second gate contact in the first direction away from the gate electrode of the second transistor of the first transistor type;program instructions for defining a third gate contact defined to physically contact the third gate level feature, wherein the third gate level feature has an extension distance extending away from the third gate contact in the first direction away from the gate electrode of the second transistor of the second transistor type;program instructions for defining a fourth gate contact defined to physically contact the fourth gate level feature, wherein the fourth gate level feature has an extension distance extending away from the fourth gate contact in the first direction away from the gate electrode of the third transistor of the first transistor type;program instructions for defining a fifth gate contact defined to physically contact the fifth gate level feature, wherein the fifth gate level feature has an extension distance extending away from the fifth gate contact in the first direction away from the gate electrode of the third transistor of the second transistor type; andprogram instructions for defining a sixth gate contact defined to physically contact the sixth gate level feature,wherein at least two of the extension distances of the second, third, fourth, and fifth gate level features are different.
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