IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0603935
(2006-11-22)
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등록번호 |
US-8569876
(2013-10-29)
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발명자
/ 주소 |
- Grinman, Andrey
- Ovrutsky, David
- Rosenstein, Charles
- Oganesian, Vage
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출원인 / 주소 |
|
대리인 / 주소 |
Lerner, David, Littenberg, Krumholz & Mentlik, LLP
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인용정보 |
피인용 횟수 :
0 인용 특허 :
38 |
초록
▼
A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to
A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.
대표청구항
▼
1. A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plural
1. A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface;at least one packaging layer containing silicon and formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface;a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads; anda second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer,wherein the die has a thickness extending from the first surface to the second surface, and wherein the first ball grid array is aligned with the second ball grid array in a direction of the thickness of the die. 2. A chip-sized, wafer level packaged device according to claim 1 and wherein said at least one packaging layer comprises a plurality of packaging layers. 3. A chip-sized, wafer level packaged device according to claim 2 and wherein said plurality of packaging layers are disposed on the same side of said die. 4. A chip-sized wafer level packaged device according to claim 1 and wherein said device is a DRAM device. 5. A chip-sized wafer level packaged device according to claim 1 and also comprising a first compliant layer, formed over said packaging layer and underlying said first ball grid array. 6. A chip-sized wafer level packaged device according to claim 5, wherein said first conductors are formed over said first compliant layer and are underlying said first ball grid array. 7. A chip-sized wafer level packaged device according to claim 5 and wherein said first compliant layer includes at least one of silicone or a polymeric dielectric material. 8. A chip-sized wafer level packaged device according to claim 7 and wherein said polymeric material comprises a polyimide. 9. A chip-sized wafer level packaged device according to claim 5 and also comprising a second compliant layer, formed over said first surface of said die and underlying said second ball grid array. 10. A chip-sized wafer level packaged device according to claim 9, wherein said second conductors are formed over said second compliant layer and are underlying said second ball grid array. 11. A chip-sized wafer level packaged device according to claim 9 and wherein said first compliant layer includes at least one of silicone or a polymeric dielectric material. 12. A chip-sized wafer level packaged device according to claim 11 and wherein said polymeric material comprises a polyimide. 13. A chip-sized wafer level packaged device according to claim 1 and wherein alpha-particle shielding is provided between at least one of said first or second ball grid arrays and said device. 14. A chip-sized wafer level packaged device according to claim 1, wherein said at least one packaging layer includes a first packaging layer, said packaged device further comprising: a second packaging layer formed over said second surface of said die, wherein said first ball grid array is formed on said first packaging layer and said second ball grid array is formed on said second packaging layer. 15. A chip-sized wafer level packaged device according to claim 14, further comprising: first compliant layer formed on said first packaging layer and underlying said first ball grid array;second compliant layer formed on said second packaging layer and underlying said second ball grid array. 16. A chip-sized wafer level packaged device according to claim 15, wherein at least one of said compliant layers provides alpha-particle shielding between at least one of said first or second ball grid arrays and said device. 17. A chip-sized wafer level packaged device according to claim 15, wherein at least one of said compliant layers comprises a layer of an electrophoretic material. 18. A chip-sized, wafer level packaged device according to claim 1, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. 19. A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface;at least one packaging layer formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface;a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads;a second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer; anda compliant electrophoretic coating layer underlying at least one of said first or second ball grid arrays,wherein the die has a thickness extending from the first surface to the second surface, and wherein the first ball grid array is aligned with the second ball grid array in a direction of the thickness of the die. 20. A chip-sized wafer level packaged device according to claim 19 and wherein said at least one packaging layer contains silicon. 21. A chip-sized wafer level packaged device according to claim 19 and wherein said compliant electrophoretic coating layer provides alpha-particle shielding between the at least one of said first or second ball grid arrays and said device. 22. A chip-sized wafer level packaged device according to claim 19 and wherein said device is a DRAM device. 23. A chip-sized, wafer level packaged device according to claim 19 and wherein said at least one packaging layer comprises a plurality of packaging layers. 24. A chip-sized, wafer level packaged device according to claim 23 and wherein said plurality of packaging layers are disposed on the same side of said die. 25. A chip-sized wafer level packaged device according to claim 19, and also comprising metal connections formed over said compliant electrophoretic coating layer and underlying the at least one of said first or second ball grid arrays, said metal connections providing electrical contact between the at least one of said first or second ball grid arrays and said device. 26. A chip-sized wafer level packaged device according to claim 19 and wherein said compliant electrophoretic coating layer includes at least one of silicone or a polymeric dielectric material. 27. A chip-sized wafer level packaged device according to claim 26 and wherein said polymeric material comprises a polyimide. 28. A chip-sized wafer level packaged device according to claim 19, wherein said at least one packaging layer includes a first packaging layer, said packaged device further comprising: a second packaging layer formed over said second surface of said die, wherein said first ball grid array is formed on said first packaging layer and said second ball grid array is formed on said second packaging layer. 29. A chip-sized wafer level packaged device according to claim 28, wherein said compliant electrophoretic coating layer comprises: first compliant electrophoretic coating layer formed on said first packaging layer and underlying said first ball grid array;second compliant electrophoretic coating layer formed on said second packaging layer and underlying said second ball grid array. 30. A chip-sized wafer level packaged device according to claim 29, wherein said first and second electrophoretic coating layers provide alpha-particle shielding between said first and second ball grid arrays and said device. 31. A chip-sized, wafer level packaged device according to claim 19, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. 32. Stacked chip-sized, wafer level packaged devices comprising: at least first and second chip-sized wafer level packaged devices each including: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface,at least one packaging layer containing silicon and formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface,a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads, anda second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer, andwherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer; andsaid first ball grid array of said first device being coupled to said second ball grid array of said second device. 33. Stacked chip-sized, wafer level packaged devices according to claim 32 and wherein said at least one packaging layer comprises a plurality of packaging layers. 34. Stacked chip-sized, wafer level packaged devices according to claim 33 and wherein said plurality of packaging layers are disposed on the same side of said portion of said semiconductor wafer. 35. A chip-sized wafer level packaged device according to claim 32 and wherein said device is a DRAM device. 36. Stacked chip-sized, wafer level packaged devices comprising: at least first and second chip-sized wafer level packaged devices each including: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including a device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface,at least one packaging layer formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface,a first ball grid array formed over said surface of said at least one packaging layer and being electrically coupled to said first bond pads,a second ball grid array formed over said second surface of said die and being electrically coupled to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer,wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer, anda compliant electrophoretic coating layer underlying at least one of said first or second ball grid arrays; andsaid first ball grid array of said first device being coupled to said second ball grid array of said second device. 37. Stacked chip-sized, wafer level packaged devices according to claim 36 and wherein said at least one packaging layer contains silicon. 38. Stacked chip-sized, wafer level packaged devices according to claim 36 and wherein said compliant electrophoretic coating layer provides alpha-particle shielding between the at least one of said first or second ball grid arrays and said device. 39. Stacked chip-sized, wafer level packaged devices according to claim 36 and wherein said device is a DRAM device. 40. A chip-sized wafer level packaged device comprising: a die severed being a portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface;a packaging layer formed over said first surface and remote from said second surface of said die, said packaging layer comprising a material having thermal expansion characteristics similar to those of said die, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface;a plurality of first interconnects formed over said surface of said packaging layer and being electrically connected to said first bond pads; anda plurality of second interconnects formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer,wherein the die has a thickness extending from the first surface to the second surface, and wherein the plurality of first interconnects is aligned with the plurality of the second interconnects in a direction of the thickness of the die. 41. A chip-sized wafer level packaged device according to claim 40 and wherein at least one of said plurality of said first interconnects or said plurality of said second interconnects comprise ACF attachable interconnects. 42. A chip-sized wafer level packaged device according to claim 41 and wherein said ACF attachable interconnects are formed of copper. 43. A chip-sized wafer level packaged device according to claim 40 and also comprising: a printed circuit board including interconnects; anda conductive film bonding said interconnects of said printed circuit board to at least one of said plurality of first interconnects or said plurality of second interconnects. 44. A chip-sized wafer level packaged device according to claim 43 and wherein said conductive film comprises an anisotropic conductive film. 45. A chip-sized wafer level packaged device according to claim 40, wherein said semiconductor wafer contains at least one of silicon or Gallium Arsenide. 46. A chip-sized wafer level packaged device according to claim 40, wherein said packaging layer is adhered to said die by an adhesive, said adhesive having thermal expansion characteristics similar to those of said packaging layer. 47. A chip-sized wafer level packaged device according to claim 40 and wherein said packaging layer comprises silicon. 48. A chip-sized wafer level packaged device according to claim 40 and wherein said device includes a memory device. 49. A chip-sized wafer level packaged device according to claim 40, wherein said packaging layer includes a first packaging layer, said packaged device further comprising: a first compliant layer provided on said first packaging layer and underlying said plurality of first interconnects;a second packaging layer formed over said second surface of said die, wherein said plurality of second interconnects are formed over said second packaging layer; anda second compliant layer provided in said second packaging layer and underlying said plurality of second interconnects. 50. A chip-sized wafer level packaged device according to claim 49, wherein said compliant layers comprise electrophoretic material for providing alpha-particle shielding between said first and second interconnects and said device. 51. A chip-sized, wafer level packaged device according to claim 40, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. 52. A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface;at least one packaging layer containing silicon and formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface;a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads; anda second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer,wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer. 53. A chip-sized, wafer level packaged device according to claim 52 and wherein said at least one packaging layer comprises a plurality of packaging layers. 54. A chip-sized, wafer level packaged device according to claim 53 and wherein said plurality of packaging layers are disposed on the same side of said die. 55. A chip-sized wafer level packaged device according to claim 52 and wherein said device is a DRAM device. 56. A chip-sized wafer level packaged device according to claim 52 and also comprising a first compliant layer, formed over said packaging layer and underlying said first ball grid array. 57. A chip-sized wafer level packaged device according to claim 56, wherein said first conductors are formed over said first compliant layer and are underlying said first ball grid array. 58. A chip-sized wafer level packaged device according to claim 56 and wherein said first compliant layer includes at least one of silicone or a polymeric dielectric material. 59. A chip-sized wafer level packaged device according to claim 58 and wherein said polymeric material comprises a polyimide. 60. A chip-sized wafer level packaged device according to claim 56 and also comprising a second compliant layer, formed over said first surface of said die and underlying said second ball grid array. 61. A chip-sized wafer level packaged device according to claim 60, wherein said second conductors are formed over said second compliant layer and are underlying said second ball grid array. 62. A chip-sized wafer level packaged device according to claim 60 and wherein said first compliant layer includes at least one of silicone or a polymeric dielectric material. 63. A chip-sized wafer level packaged device according to claim 62 and wherein said polymeric material comprises a polyimide. 64. A chip-sized wafer level packaged device according to claim 52 and wherein alpha-particle shielding is provided between at least one of said first or second ball grid arrays and said device. 65. A chip-sized wafer level packaged device according to claim 52, wherein said at least one packaging layer includes a first packaging layer, said packaged device further comprising: a second packaging layer formed over said second surface of said die, wherein said first ball grid array is formed on said first packaging layer and said second ball grid array is formed on said second packaging layer. 66. A chip-sized wafer level packaged device according to claim 65, further comprising: first compliant layer formed on said first packaging layer and underlying said first ball grid array; andsecond compliant layer formed on said second packaging layer and underlying said second ball grid array. 67. A chip-sized wafer level packaged device according to claim 66, wherein at least one of said compliant layers provides alpha-particle shielding between at least one of said first or second ball grid arrays and said device. 68. A chip-sized wafer level packaged device according to claim 66, wherein at least one of said compliant layers comprises a layer of an electrophoretic material. 69. A chip-sized, wafer level packaged device according to claim 52, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. 70. A chip-sized, wafer level packaged device comprising: a die being a severed portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface;at least one packaging layer formed over said first surface and remote from said second surface, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface;a first ball grid array formed over said surface of said at least one packaging layer and being electrically connected to said first bond pads;a second ball grid array formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer; anda compliant electrophoretic coating layer underlying at least one of said first or second ball grid arrays,wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer. 71. A chip-sized wafer level packaged device according to claim 70 and wherein said at least one packaging layer contains silicon. 72. A chip-sized wafer level packaged device according to claim 70 and wherein said compliant electrophoretic coating layer provides alpha-particle shielding between the at least one of said first or second ball grid arrays and said device. 73. A chip-sized wafer level packaged device according to claim 70 and wherein said device is a DRAM device. 74. A chip-sized, wafer level packaged device according to claim 70 and wherein said at least one packaging layer comprises a plurality of packaging layers. 75. A chip-sized, wafer level packaged device according to claim 74 and wherein said plurality of packaging layers are disposed on the same side of said die. 76. A chip-sized wafer level packaged device according to claim 70, and also comprising metal connections formed over said compliant electrophoretic coating layer and underlying the at least one of said first or second ball grid arrays, said metal connections providing electrical contact between the at least one of said first or second ball grid arrays and said device. 77. A chip-sized wafer level packaged device according to claim 70 and wherein said compliant electrophoretic coating layer includes at least one of silicone or a polymeric dielectric material. 78. A chip-sized wafer level packaged device according to claim 77 and wherein said polymeric material comprises a polyimide. 79. A chip-sized wafer level packaged device according to claim 70, wherein said at least one packaging layer includes a first packaging layer, said packaged device further comprising: a second packaging layer formed over said second surface of said die, wherein said first ball grid array is formed on said first packaging layer and said second ball grid array is formed on said second packaging layer. 80. A chip-sized wafer level packaged device according to claim 79, wherein said compliant electrophoretic coating layer comprises: first compliant electrophoretic coating layer formed on said first packaging layer and underlying said first ball grid array; andsecond compliant electrophoretic coating layer formed on said second packaging layer and underlying said second ball grid array. 81. A chip-sized wafer level packaged device according to claim 80, wherein said first and second electrophoretic coating layers provides alpha-particle shielding between said first and second ball grid arrays and said device. 82. A chip-sized, wafer level packaged device according to claim 70, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors. 83. A chip-sized wafer level packaged device comprising: a die severed being a portion of a semiconductor wafer, said die having a first surface and a second surface remote from said first surface, said die including at least one device integrally therein, a plurality of first bond pads and a plurality of second bond pads, each of said first and second bond pads being adjacent to said first surface;a packaging layer formed over said first surface and remote from said second surface of said die, said packaging layer comprising a material having thermal expansion characteristics similar to those of said die, said at least one packaging layer overlying the second bond pads and having a surface remote from said first surface;a plurality of first interconnects formed over said surface of said packaging layer and being electrically connected to said first bond pads; anda plurality of second interconnects formed over said second surface of said die and being electrically connected to said second bond pads by conductors extending through an opening in said die to first surfaces of said second bond pads remote from said at least one packaging layer,wherein said first surfaces of said second bond pads face said second surface of the die, wherein said second bond pads have second surfaces opposite said first surfaces of the second bond pads, and said second surfaces of the second bond pads face said at least one packaging layer. 84. A chip-sized wafer level packaged device according to claim 83 and wherein at least one of said plurality of said first interconnects or said plurality of said second interconnects comprise ACF attachable interconnects. 85. A chip-sized wafer level packaged device according to claim 84 and wherein said ACF attachable interconnects are formed of copper. 86. A chip-sized wafer level packaged device according to claim 83 and also comprising: a printed circuit board including interconnects; anda conductive film bonding said interconnects of said printed circuit board to at least one of said plurality of first interconnects or said plurality of second interconnects. 87. A chip-sized wafer level packaged device according to claim 86 and wherein said conductive film comprises an anisotropic conductive film. 88. A chip-sized wafer level packaged device according to claim 83, wherein said semiconductor wafer contains at least one of silicon or Gallium Arsenide. 89. A chip-sized wafer level packaged device according to claim 83, wherein said packaging layer is adhered to said die by an adhesive, said adhesive having thermal expansion characteristics similar to those of said packaging layer. 90. A chip-sized wafer level packaged device according to claim 83 and wherein said packaging layer comprises silicon. 91. A chip-sized wafer level packaged device according to claim 83 and wherein said device includes a memory device. 92. A chip-sized wafer level packaged device according to claim 83, wherein said packaging layer includes a first packaging layer, said packaged device further comprising: a first compliant layer provided on said first packaging layer and underlying said plurality of first interconnects;a second packaging layer formed over said second surface of said die, wherein said plurality of second interconnects are formed over said second packaging layer; anda second compliant layer provided in said second packaging layer and underlying said plurality of second interconnects. 93. A chip-sized wafer level packaged device according to claim 92, wherein said compliant layers comprise electrophoretic material for providing alpha-particle shielding between said first and second interconnects and said device. 94. A chip-sized, wafer level packaged device according to claim 83, wherein said conductors are first conductors, said device further comprising a plurality of second conductors extending through an opening in said at least one packaging layer to surfaces of said first bond pads adjacent said at least one packaging layer, wherein each of said second conductors is electrically insulated from each of said first conductors.
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