There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crysta
There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
대표청구항▼
1. A semiconductor device comprising: an island-like single crystalline semiconductor layer over a silicon substrate with a bonded interface interposed between the island-like single crystalline semiconductor layer and the silicon substrate, the island-like single crystalline semiconductor layer com
1. A semiconductor device comprising: an island-like single crystalline semiconductor layer over a silicon substrate with a bonded interface interposed between the island-like single crystalline semiconductor layer and the silicon substrate, the island-like single crystalline semiconductor layer comprising part of a single crystalline silicon substrate different from the silicon substrate and having at least a channel formation region and source and drain regions;an insulating film formed on the island-like single crystalline semiconductor layer;a gate electrode formed over the channel formation region with the insulating film interposed therebetween;side walls formed adjacent to side surfaces of the gate electrode; andan interlayer insulating film comprising silicon nitride formed over the gate electrode and the side walls, wherein a top face of the island-like single crystalline semiconductor layer under the gate electrode is thermally oxidized to form the insulating film,wherein a bottom face of the island-like single crystalline semiconductor layer is thermally oxidized to form a silicon oxide layer in contact with the bottom face,wherein each of the source and drain regions includes at least a portion that extends through an entire thickness of the island-like single crystalline semiconductor layer such that the source and drain regions contact the silicon oxide layer, andwherein an upper portion of the gate electrode and upper portions of the source and drain regions comprise a metal silicide. 2. The semiconductor device according to claim 1, wherein the metal silicide is cobalt silicide. 3. The semiconductor device according to claim 1, wherein the island-like single crystalline semiconductor layer is hydrogenated. 4. The semiconductor device according to claim 1, wherein the source and drain regions are in contact with the silicon oxide layer. 5. The semiconductor device according to claim 1, wherein the silicon oxide layer is 0.05 to 0.5 μm thick. 6. The semiconductor device according to claim 1, wherein the side walls contact side surfaces of the gate electrode and the insulating film. 7. The semiconductor device according to claim 1, wherein the silicon oxide layer contains a halogen. 8. The semiconductor device according to claim 1, wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower. 9. A semiconductor device comprising: an island-like single crystalline semiconductor layer over a silicon substrate with a bonded interface interposed between the island-like single crystalline semiconductor layer and the silicon substrate, the island-like single crystalline semiconductor layer comprising part of a single crystalline silicon substrate different from the silicon substrate and having at least a channel formation region, source and drain regions, and LDD regions;an insulating film formed on the island-like single crystalline semiconductor layer;a gate electrode formed over the channel formation region with the insulating film interposed therebetween;side walls formed adjacent to side surfaces of the gate electrode, wherein the LDD regions are located below the side walls with the insulating film interposed therebetween; andan interlayer insulating film comprising silicon nitride formed over the gate electrode and the side walls, wherein a top face of the island-like single crystalline semiconductor layer under the gate electrode is thermally oxidized to form the insulating film,wherein a bottom face of the island-like single crystalline semiconductor layer is thermally oxidized to form a silicon oxide layer in contact with the bottom face,wherein each of the source and drain regions includes at least a portion that extends through an entire thickness of the island-like single crystalline semiconductor layer such that the source and drain regions contact the silicon oxide layer, andwherein an upper portion of the gate electrode and upper portions of the source and drain regions comprise a metal silicide. 10. The semiconductor device according to claim 9, wherein the metal silicide is cobalt silicide. 11. The semiconductor device according to claim 9, wherein the island-like single crystalline semiconductor layer is hydrogenated. 12. The semiconductor device according to claim 9, wherein the source and drain regions are in contact with the silicon oxide layer. 13. The semiconductor device according to claim 9, wherein the silicon oxide layer is 0.05 to 0.5 μm thick. 14. The semiconductor device according to claim 9, wherein the side walls contact side surfaces of the gate electrode and the insulating film. 15. The semiconductor device according to claim 9, wherein the LDD regions are in contact with the silicon oxide layer. 16. The semiconductor device according to claim 9, wherein the silicon oxide layer contains a halogen. 17. The semiconductor device according to claim 9, wherein the maximum of the thickness of the island-like single crystalline semiconductor layer is 50 nm or lower.
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