A variable gain amplifier includes a first transistor having a base for receiving a radio frequency (“RF”) input signal. A first differential transistor pair is coupled in parallel to a second transistor. The first differential transistor pair and the second transistor are coupled to a collector of
A variable gain amplifier includes a first transistor having a base for receiving a radio frequency (“RF”) input signal. A first differential transistor pair is coupled in parallel to a second transistor. The first differential transistor pair and the second transistor are coupled to a collector of the first transistor and to an output node of the first variable gain amplifier. Each transistor of the first differential transistor pair is configured to receive a control signal at its respective gate for adjusting a gain of the variable gain amplifier.
대표청구항▼
1. A variable gain amplifier, comprising: a first input transistor having a base for receiving a first radio frequency (RF) input signal;a second input transistor having a base for receiving a differential RF signal;a first plurality of differential transistor pairs, said first plurality of differen
1. A variable gain amplifier, comprising: a first input transistor having a base for receiving a first radio frequency (RF) input signal;a second input transistor having a base for receiving a differential RF signal;a first plurality of differential transistor pairs, said first plurality of differential transistor pairs connected in parallel to a first biasing transistor, the first biasing transistor configured to receive a bias voltage at its gate to keep the first biasing transistor in a conducting state;a second plurality of differential transistor pairs, said second plurality of differential transistor pairs connected in parallel to a second biasing transistor, the second biasing transistor configured to receive a bias voltage at its gate to keep the second biasing transistor in a conducting state;a first output transistor having its gate connected to the drain of one transistor in each differential transistor pair of the first plurality of differential transistor pairs and the drain of the first biasing transistor, and the first output transistor having its drain connected to an output terminal for delivering an output based on the first RF signal; anda second output transistor having its gate connected to the drain of one transistor in each differential transistor pair of the second plurality of differential transistor pairs and the drain of the second biasing transistor, and the second output transistor having its drain connected to an output terminal for delivering an output based on the differential RF signal;wherein the first and second pluralities of differential transistor pairs are configured in a cascade configuration as a single device having individually controllable fingers to provide a wideband gain control of the variable gain amplifier. 2. The variable gain amplifier of claim 1, further comprising: a first RC network coupled to the base of the first input transistor; anda second RC network coupled to the base of the second input transistor, the first and second RC networks for blocking a DC bias voltages. 3. The variable gain amplifier of claim 1, wherein the emitters of the first input transistor and the second input transistor are coupled to ground via a drain of a transistor having a source coupled to ground. 4. The variable gain amplifier of claim 1, further comprising a control circuit coupled to each of said differential transistor pairs, said control circuit operative to generate a control word for selectively turning on and off transistors in each of said differential transistor pairs, to thereby control the gain of said variable gain amplifier. 5. The variable gain amplifier of claim 4, wherein the control word comprises multiple bits, and wherein the control circuit applies to a transistor of each differential transistor pair a certain bit in the bit order of the control word. 6. The variable gain amplifier of claim 4, wherein each of the differential transistor pairs has the same size. 7. A method of adjusting a gain of a variable gain amplifier, comprising: receiving a first radio frequency (RE) signal at a base of a first input transistor having a collector coupled to a first at least one differential transistor pair and to a first biasing transistor coupled in parallel with the first at least one differential transistor pair;arranging the first at least one differential transistor pair in a cascode configuration as a single device having individually controllable fingers to provide a wideband method of gain control;receiving a control signal at a gate of each of the transistors of the first at least one differential transistor pair to adjust the gain of the variable gain amplifier; andoutputting a first output RF signal from a node coupled to an emitter of a first output transistor having a base coupled to the first biasing transistor and to at least one of the transistors of each of the first at least one differential transistor pair. 8. The method of claim 7, further comprising: receiving a second differential RF signal at a base of a second input transistor having a collector coupled to a second at least one differential transistor pair and to a second biasing transistor coupled in parallel with the second at least one differential transistor pair;arranging the second at least one differential transistor pair in a cascode configuration as a single device having individually controllable fingers to provide a wideband method of gain control;receiving a control signal at a gate of each of the transistors of the second at least one differential transistor pair to adjust the gain of the variable gain amplifier; andoutputting a second output RF signal from a node coupled to an emitter of a second output transistor having a base coupled to the second biasing transistor and to at least one of the transistors of each of the second at least one differential transistor pair. 9. The method of claim 8, further comprising blocking a DC bias voltage of the first RF signal at a first RC network coupled to the base of the first input transistor. 10. A variable gain amplifier, comprising: a first input transistor having a base configured to receive a first radio frequency (RF) signal;a second input transistor having a base configured to receive a differential RF signal;a first plurality of differential transistor pairs, each differential transistor pair of said first plurality of differential transistor pairs having a common source coupled to a collector of the first input transistor; wherein each differential transistor pair in said first plurality has one transistor whose drain is coupled with the drain of another transistor of said first plurality, the common drains of corresponding transistors of the first plurality defining an output node for an output RF signal corresponding to said first RF signal;a second plurality of differential transistor pairs, each differential transistor pair of said second plurality of differential transistor pairs having a common source coupled to a collector of the second input transistor; wherein each differential transistor pair in said second plurality has one transistor whose drain is coupled with the drain of another transistor of said second plurality, the common drains of corresponding transistors of the second plurality defining a second output node for an output RF signal corresponding to said differential RF signal,wherein said first and second pluralities of differential transistor pairs are arranged in parallel; andwherein a control circuit applies control signals to the gates of each transistor in each of said first and second pluralities of differential transistor pairs for selectively adjusting a voltage gain at the output nodes of the variable gain amplifier and the first and second pluralities of differential transistor pairs are configured in a cascode configuration as a single device having individually controllable fingers to provide a wideband pain control of the variable pain amplifier. 11. The variable gain amplifier of claim 10, further comprising: a first conducting transistor whose source is coupled to the collector of the first transistor, and whose drain is coupled to the common drains of corresponding ones of the transistors of the first plurality;a second conducting transistor whose source is coupled to the collector of the second transistor, and whose drain is coupled to the common drains of corresponding ones of the transistors of the second plurality. 12. The variable gain amplifier of claim 11, wherein: each differential transistor pair in said first plurality has another transistor whose drain is coupled to a supply voltage. 13. The variable gain amplifier of claim 10, wherein said first and second transistors are bipolar junction transistors. 14. The variable gain amplifier of claim 13, wherein said first and second pluralities of differential transistor pairs are MOSFETs. 15. The variable gain amplifier of claim 14, wherein said first and second conducting transistors are MOSFETs. 16. A variable gain amplifier, comprising: a first transistor having a base for receiving a radio frequency (RF) input signal;a first differential transistor pair coupled in parallel to a second transistor, the first differential transistor pair and the second transistor coupled to a collector of the first transistor and to an output node of the variable gain amplifier;a third transistor having a base coupled to a drain of the second transistor and to at least one transistor of the first differential transistor pair;a fourth transistor having a base for receiving the RF input signal and an emitter coupled to an emitter of the first transistor;a second differential transistor pair coupled in parallel to a fifth transistor, the second differential transistor pair and the fifth transistor coupled to a collector of the fourth transistor;a sixth transistor having a base coupled to a drain of the fifth transistor and to at least one transistor of the second differential transistor pair;a third differential transistor pair coupled in parallel to the first differential transistor pair and to the second transistor;a fourth differential transistor pair coupled in parallel to the second differential transistor pair and to the fifth transistor;a control circuit coupled to each of the differential transistor pairs, said control circuit operative to generate a control word for selectively turning on and off transistors in each of said differential transistor pairs, to thereby control the gain of the variable gain amplifier;wherein each transistor of each differential transistor pair is configured to receive a control signal from said control circuit at its respective gate for adjusting a gain of the variable gain amplifier; andwherein each of the differential transistor pairs has the same size.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (11)
Williams, Richard K., Cascode current sensor for discrete power semiconductor devices.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.