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Dynamic load balancing of instructions for execution by heterogeneous processing engines

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/46
출원번호 US-0831873 (2007-07-31)
등록번호 US-8578387 (2013-11-05)
발명자 / 주소
  • Mills, Peter C.
  • Oberman, Stuart F.
  • Lindholm, John Erik
  • Liu, Samuel
출원인 / 주소
  • Nvidia Corporation
대리인 / 주소
    Patterson & Sheridan, L.L.P.
인용정보 피인용 횟수 : 2  인용 특허 : 21

초록

An embodiment of a computing system is configured to process data using a multithreaded SIMD architecture that includes heterogeneous processing engines to execute a program. The program is constructed of various program instructions. A first type of the program instructions can only be executed by

대표청구항

1. A computer-implemented method for dynamically load balancing instruction execution in a single-instruction multiple-data (SIMD) architecture with heterogeneous processing engines, comprising: computing, prior to assigning instructions included in a set of unassigned instructions, a first initial

이 특허에 인용된 특허 (21)

  1. Eilert Catherine K. (Wappingers Falls NY) Pierce Bernard R. (Poughkeepsie NY), Apparatus and method for managing a server workload according to client performance goals in a client/server data proces.
  2. Hirata Hiroaki (Kyoto JPX) Nishimura Akio (Osaka JPX), Apparatus for simultaneously scheduling instruction from plural instruction streams into plural instruction execution un.
  3. Hirata Hiroaki (Kyoto-fu JPX) Nishimura Akio (Osaka-fu JPX), Apparatus for simultaneously scheduling instructions from plural instruction stream into plural instruction executions u.
  4. Lipasti Mikko Herman, Circuit arrangement and method of dispatching instructions to multiple execution units.
  5. Eisen, Susan Elizabeth; Phillips, James Edward, Data processing system and method for implementing an efficient out-of-order issue mechanism.
  6. Doraswamy Naganand ; Ramakrishnan Kadangode K., Load balancing based on queue length, in a network of processor stations.
  7. David Andrew Schroter, Measured, allocation of speculative branch instructions to processor execution units.
  8. Harchol-Balter Mor ; Crovella Mark E., Method and apparatus for assigning tasks in a distributed server system.
  9. Rudd, Kevin W.; Walterscheidt, Udo, Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution.
  10. Beaumont,Mark, Method for using filtering to load balance a loop of parallel processing elements.
  11. Favor John G., Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instructio.
  12. Miyake,Hideo; Suga,Atsuhiro; Nakamura,Yasuki; Takebe,Yoshimasa, Parallel Processor efficiently executing variable instruction word.
  13. Alpert Donald B. (Santa Clara CA) Avnon Dror (Milpitas CA) Ben-Meir Amos (Fremont CA) Talmudi Ran (Ra\Anana ILX), Partially decoded instruction cache.
  14. Lindholm,John E.; Coon,Brett W., Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operations.
  15. Coon, Brett W.; Lindholm, John Erik; Mills, Peter C.; Nickolls, John R., Processing an indirect branch instruction in a SIMD architecture.
  16. Kelly, Mark; Newman, Charles Edward, Processor assignment in multi-processor systems.
  17. Freund Richard F., Scheduling framework for a heterogeneous computer network.
  18. Mills,Peter C.; Lindholm,John Erik; Coon,Brett W.; Tarolli,Gary M.; Burgess,John Matthew, Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching.
  19. Rouet, Christian; Bastos, Rui M.; Kilgariff, Emmett M., Scheduling program instruction execution by using fence instructions.
  20. Byers Larry L. (Apple Valley MN) De Subijana Joseba M. (Minneapolis MN) Michaelson Wayne A. (Circle Pines MN), System and method for executing branch instructions wherein branch target addresses are dynamically selectable under pro.
  21. Smith Bradley J. (Converse TX), Weighted system and method for spatial allocation of a parallel load.

이 특허를 인용한 특허 (2)

  1. Miller, Howard; Brunner, Ralph, Methods and apparatuses for load balancing between multiple processing units.
  2. Krig, Scott; Morrison, Teresa, Scalable compute fabric.
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