Method and system for forming conductive bumping with copper interconnection
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/44
출원번호
US-0645448
(2012-10-04)
등록번호
US-8581366
(2013-11-12)
우선권정보
CN-2008 1 0040739 (2008-07-15)
발명자
/ 주소
Xiao, De Yuan
Chen, Guo Qing
출원인 / 주소
Semiconductor Manufacturing International (Shanghai) Corporation
대리인 / 주소
Kilpatrick Townsend and Stockton LLP
인용정보
피인용 횟수 :
0인용 특허 :
27
초록▼
A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material.
A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material.
대표청구항▼
1. A method for making an integrated circuit system with one or more copper interconnects, the one or more copper interconnects being conductively connected with a substrate, the method comprising: depositing and patterning a first dielectric layer to form a first via;filling the first via through t
1. A method for making an integrated circuit system with one or more copper interconnects, the one or more copper interconnects being conductively connected with a substrate, the method comprising: depositing and patterning a first dielectric layer to form a first via;filling the first via through the first dielectric layer with a copper material;depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via;forming a diffusion barrier layer, the diffusion barrier layer at least partially filling the second via through the second dielectric layer, at least a first part of the diffusion barrier layer in direct contact with the copper material, at least a second part of the diffusion barrier layer in direct contact with the second dielectric layer;depositing and patterning a photoresist layer on the diffusion barrier layer;at least partially filling the second via with a metal material, the metal material being conductively connected to the copper material through the diffusion barrier layer; andconductively connecting the metal material with the substrate,wherein the metal material comprises gold, silver, nickel, or copper. 2. The method of claim 1, wherein the first dielectric layer can be fluorinated silica glass (FSG) or carbonized silicon dioxide. 3. The method of claim 1, wherein the second dielectric layer comprises a first sub-layer and a second sub-layer; wherein the first sub-layer is passivation oxide or silicon rich oxide (SRO) and the second sub-layer overlaying the first sub-layer is passivation SiON, Nitride, benzocyclobutene (BCB) or polyimide. 4. The method of claim 3, wherein the first sub-layer is first deposited and the second sub-layer is deposited on top of the first sub-layer. 5. The method of claim 1, wherein the diffusion barrier layer comprises at least one material layer selected from a group consisting of Ta, TaN, TaN/Ta, TiN, TiSiN, W, TiW, and WN. 6. The method of claim 1 further comprising forming a barrier layer on the inner surface of the first via before filling copper material. 7. The method of claim 6, wherein the barrier layer comprises TaN. 8. The method of claim 1 further comprising an annealing process at a temperature between 200° C. and 600° C. 9. The method of claim 1, wherein the substrate is a PCB board, an interposer, or a glass substrate. 10. The method of claim 1, wherein the diffusion barrier layer comprises a metal seed layer comprising gold, silver, nickel, or copper. 11. The method of claim 10, wherein the metal seed layer is deposited after the deposition of the diffusion barrier layer.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (27)
Hosseini, Khalil; Stecher, Matthias, Electronic device and method for production.
Braeckelmann Gregor ; Venkatraman Ramnath ; Herrick Matthew Thomas ; Simpson Cindy R. ; Fiordalice Robert W. ; Denning Dean J. ; Jain Ajay ; Capasso Cristiano, Method for forming a semiconductor device.
Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
Edelstein, Daniel C.; Andricacos, Panayotis C.; Cotte, John M.; Deligianni, Hariklia; Magerlein, John H.; Petrarca, Kevin S.; Stein, Kenneth J.; Volant, Richard P., Method of fabricating a high Q factor integrated circuit inductor.
Shigeru Harada JP; Yoshifumi Takata JP; Junko Izumitani JP, Semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion and method for fabricating the same.
Maniar Papu D. (Austin TX) Moazzami Reza (Austin TX) Mogab C. Joseph (Austin TX), Semiconductor device having a reducing/oxidizing conductive material.
Ozawa,Ken, Semiconductor device with multi-layered wiring arrangement including reinforcing patterns, and production method for manufacturing such semiconductor device.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.