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Aspects of a method and system for decoding single antenna interference cancellation (SAIC) and redundancy processing adaptation using burst process are provided. A wireless receiver may decode bit sequences based on a first decoding algorithm that may utilize redundancy in the data and that may imp

Aspects of a method and system for decoding single antenna interference cancellation (SAIC) and redundancy processing adaptation using burst process are provided. A wireless receiver may decode bit sequences based on a first decoding algorithm that may utilize redundancy in the data and that may impose physical constraints. The receiver may also decode a received bit sequence based on a second decoding algorithm that utilizes SAIC. Received data may be processed in a burst process portion in either decoding algorithm. Burst processed data from one of the decoding algorithms may be selected based on signal-to-noise ratio and/or received signal level measurements. The selected burst processed data may be communicated to a frame processing portion of the corresponding decoding algorithm.

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1. A method for signal processing, the method comprising: processing, with a first decoding device, a bit sequence using a portion of a first decoding algorithm to generate a first processed bit sequence, the first decoding algorithm utilizing redundancy and at least one physical constraint associat

1. A method for signal processing, the method comprising: processing, with a first decoding device, a bit sequence using a portion of a first decoding algorithm to generate a first processed bit sequence, the first decoding algorithm utilizing redundancy and at least one physical constraint associated with the bit sequence;processing, with a second decoding device, the bit sequence using a portion of a second decoding algorithm to generate a second processed bit sequence, the second decoding algorithm utilizing single antenna interference cancellation; andselecting the first processed bit sequence or the second processed bit sequence based on one or more signal characteristics associated with each of the first and second processed bit sequences. 2. The method of claim 1, further comprising: applying the selected processed first or second bit sequence to a remaining portion of the first decoding algorithm or the second decoding algorithm. 3. The method of claim 1, wherein the processing the bit sequence using the first decoding algorithm and the processing the bit sequence using the second decoding algorithm comprise applying a third processed bit sequence from a previously-processed frame during at least one of the first decoding algorithm, the second decoding algorithm, or both the first and second decoding algorithms. 4. The method of claim 1, wherein the processing the bit sequence using the first decoding algorithm comprises decoding the bit sequence using the at least one physical constraint, the at least one physical constraint being related to a type of data associated with the bit sequence. 5. The method of claim 1, wherein the selecting comprises selecting either the first processed bit sequence or the second processed bit sequence on a burst-by-burst basis. 6. The method of claim 1, wherein the selecting comprises selecting the first processed bit sequence or the second processed bit sequence based on the bit sequence with the highest signal-to-noise ratio. 7. The method of claim 1, wherein the selecting comprises calculating a signal-to-noise ratio associated with each of the first and second processed bit sequences by dividing a signal power estimate of a respective bit sequence by a noise power estimate of the respective bit sequence. 8. A machine-readable storage having stored thereon, a computer program having at least one code section for signal processing, the at least one code section being executable by a machine for causing the machine to perform steps comprising: processing a bit sequence using a portion of a first decoding algorithm to generate a first processed bit sequence, the first decoding algorithm utilizing redundancy and at least one physical constraint associated with the bit sequence;processing the bit sequence using a portion of a second decoding algorithm to generate a second processed bit sequence, the second decoding algorithm utilizing single antenna interference cancellation; andselecting the first processed bit sequence or the second processed bit sequence based on one or more signal characteristics associated with each of the first and second processed bit sequences. 9. The machine-readable storage of claim 8, wherein the at least one code section being executable by a machine for causing the machine to perform steps further comprises: applying the selected processed first or second bit sequence to a remaining portion of the first decoding algorithm or the second decoding algorithm. 10. The machine-readable storage of claim 8, wherein the processing the bit sequence using the first decoding algorithm and the processing the bit sequence the second decoding algorithm comprise applying a third processed bit sequence from a previously-processed frame during at least one of the first decoding algorithm, the second decoding algorithm, or both the first and second decoding algorithms. 11. The machine-readable storage of claim 8, wherein the processing the bit sequence using the first decoding algorithm comprises decoding the bit sequence using the at least one physical constraint, the at least one physical constraint being related to a type of data associated with the bit sequence. 12. The machine-readable storage of claim 8, wherein the selecting comprises selecting either the first processed bit sequence or the second processed bit sequence on a burst-by-burst basis. 13. The machine-readable storage of claim 8, wherein the selecting comprises selecting the first processed bit sequence or the second processed bit sequence based on the bit sequence with the highest signal-to-noise ratio. 14. The machine-readable storage of claim 8, wherein the selecting comprises calculating a signal-to-noise ratio associated with each of the first and second processed bit sequences by dividing a signal power estimate of a respective bit sequence by a noise power estimate of the respective bit sequence. 15. A system for signal processing, the system comprising: a first decoding device configured to process a bit sequence using a portion of a first decoding algorithm to generate a first processed bit sequence, the first decoding algorithm utilizing redundancy and at least one physical constraint associated with the bit sequence;a second decoding device configured to process the bit sequence using a portion of a second decoding algorithm to generate a second processed bit sequence, the second decoding algorithm utilizing single antenna interference cancellation; anda selector device configured to select the first processed bit sequence or the second processed bit sequence based on one or more signal characteristics associated with each of the first and second processed bit sequences. 16. The system of claim 15, further comprising: a processing device configured to apply the selected processed first or second bit sequence to a remaining portion of the first decoding algorithm or the second decoding algorithm. 17. The system of claim 15, wherein the first decoding device and the second decoding device are configured to apply a third processed bit sequence from a previously-processed frame during at least one of the first decoding algorithm, the second decoding algorithm, or both the first and second decoding algorithms. 18. The system of claim 15, wherein the first decoding device is configured to decode the bit sequence using the at least one physical constraint, the at least one physical constraint being related to a type of data associated with the bit sequence. 19. The system of claim 15, wherein the selector device is configured to select either the first processed bit sequence or the second processed bit sequence on a burst-by-burst basis. 20. The system of claim 15, wherein the selector device is configured to select the first processed bit sequence or the second processed bit sequence based on the bit sequence with the highest signal-to-noise ratio. 21. The system of claim 15, wherein the selector device is configured to calculate a signal-to-noise ratio associated with each of the first and second processed bit sequences by dividing a signal power estimate of a respective bit sequence by a noise power estimate of the respective bit sequence.