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Power control for information handling system having shared resources 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/00
출원번호 US-0276951 (2011-10-19)
등록번호 US-8583953 (2013-11-12)
발명자 / 주소
  • Sultenfuss, Andrew T.
출원인 / 주소
  • Dell Products, LP
대리인 / 주소
    Larson Newman, LLP
인용정보 피인용 횟수 : 15  인용 특허 : 41

초록

An information handling system includes at least two processing systems that share system resources. In response to detecting a designated event, a power control module of the information handling system can select one of a plurality of available power profiles. The power profile can be selected bas

대표청구항

1. A method comprising: detecting a first event at a first processing system of an information handling system having a plurality of system resources;in response to detecting the first event at the first processing system, determining a first power mode for a first system resource based on the first

이 특허에 인용된 특허 (41)

  1. Watts, Jr., La Vaughn F., Apparatus and method for a combination personal digital assistant and network portable device.
  2. James, Tsai; Jalfon, Marc, Apparatus and methods using intelligent wake mechanisms.
  3. Lee,Jeong Soo; Kim,Chan Dong, Apparatus for controlling standby power.
  4. Engel Gary L. (Wyoming MN) Georgeson Paul J. (Minneapolis MN) Mueller Douglas R. (Shoreview MN) Quernemoen John M. (New Brighton MN) Todd Bruce C. (Blaine MN), Automatic power control system which automatically activates and deactivates power to selected peripheral devices based.
  5. Walker Richard E. (The Woodlands TX) Bowman Kurtis J. (Cypress TX), Circuit that automatically switches between supplying a microprocessor with a first voltage and a second voltage.
  6. Watts, Jr., La Vaughn F.; Shaw, Ronald D., Combination personal data assistant and personal computing device.
  7. Watts, Jr., La Vaughn F., Combination personal data assistant and personal computing device with master slave input output.
  8. Hirosawa Toshio (Machida JPX) Ohki Masaru (Kodaira JPX) Kuwahara Yutaka (Hachioji JPX), Computer system with power control based on the operational status of terminals.
  9. Hart, Frank P., Context transferring between portable computer processor and docking station processor upon docking and undocking.
  10. Tarr, Morton, Electrical power strip for use with a computer and associated peripheral devices.
  11. Sherburne, Jr.,Robert Warren, Low power clocking systems and methods.
  12. King, Joseph D., Margining processor power supply.
  13. Mansell,David Hennah; Grisenthwaite,Richard Roy; Fearnhamm,Harry Samuel Thomas; Davies,Jeremy Piers, Method and apparatus for placing at least one processor into a power saving mode when another processor has access to a shared resource and exiting the power saving mode upon notification that the sh.
  14. Wang, Yao; Chehadeh, Mohamed; Vu, Quang, Method and apparatus for providing host resources for an electronic commerce site.
  15. Rotier Michael J. (Sunnyvale CA) Huffman William A. (Santa Cruz CA), Method and apparatus for upgrading a central processing unit and existing memory structure in a computer system.
  16. Muehsam, Gerhard, Method and configuration for effecting an interruption-free power supply operation of a system unit.
  17. Bartley Gerald K. ; Cecchi Delbert R. ; Collett Jeffrey A. ; Herman Linda S. ; Lewis David O. ; Sellers Glenn W., Method for personalizing integrated circuit devices.
  18. Watts, Jr., La Vaughn F.; Shaw, Ronald D., Method of filtering events in a combinational computing device.
  19. Watts, Jr.,La Vaughn F.; Shaw,Ronald D., Method of operating combination personal data assistant and personal computing device.
  20. Stedman, Roy W.; Sultenfuss, Andrew T.; Loadman, David, Multi-mode processing module and method of use.
  21. Ragan, Thomas Glen, Multiple function handheld device.
  22. Nakashima Tatsuya,JPX, PC card capable multiple functions and corresponding card information structures (CIS) where switch setting element selects CIS to read out based on selection signal.
  23. Shaw, Ronald D., Peripheral switching device with multiple sets of registers for supporting an ACPI full-operation state.
  24. Kuzawinski Mark J. (Maine NY) Zielinski Edward J. (Endicott NY), Power controller for permitting multiple processors to power up shared input/output devices and inhibit power down until.
  25. Munguia,Peter R., Power managed busses and arbitration.
  26. Naveh, Alon; Rotem, Efraim; Weissmann, Eliezer, Power management coordination in multi-core processors.
  27. Tupman, David, Power management for driving display with baseband portion when application portion is in low power mode.
  28. Hussain, Farooq S., Power management for multimode wireless communication device.
  29. Villanueva Peter T., Power share controller for providing continuous system peripheral bay access between at least two data processing systems on a data network with no interruption to peripheral bay operation.
  30. Polzin R. Stephen (Morgan Hill CA) Price Noah M. (Campbell CA) Takahashi Duane M. P. (San Jose CA), Printed circuit board processor card for upgrading a processor-based system.
  31. Reed Ronald G. (Colorado Springs CO) Rasper John T. (Colorado Springs CO), Process for use in rapidly producing printed circuit boards using a computer controlled plotter.
  32. Richard Cliff ; Robert Bielby, Programmable voltage regulator.
  33. Huber,Gary Douglas; Shoobe,Howard A.; Watts, Jr.,La Vaughn F., Removable personal digital assistant in a dual personal computer/personal digital assistant computer architecture.
  34. Gulick, Dale E., System and method for monitoring and controlling a power-manageable resource based upon activities of a plurality of devices.
  35. Reneris Kenneth S., System and method for using data structures to share a plurality of power resources among a plurality of devices.
  36. Terrell, II,James Richard, System clock power management for chips with multiple processing modules.
  37. Fulghum Patrick W., System for upgrading functionality of a peripheral device utilizing a removable ROM having relocatable object code.
  38. Belt Steven L. (Stevensville MI) Grabon Robert J. (Berrien Springs ; Oronoko Township ; Berrien County MI) Pandya Chandrakant H. (St. Joseph MI) Sun Jiming (St. Joseph MI) Terry-Gray Neysa K. (Lake T, System suspend on lid close and system resume on lid open.
  39. Paljug,Michael, Systems and methods for waking up wireless LAN devices.
  40. Pipes Beatrice Dee, Two computers cooperating via interconnected busses.
  41. Lee Sherman, User-removable central processing unit card for an electrical device.

이 특허를 인용한 특허 (15)

  1. Poulton, John W.; Greer, III, Thomas Hastings; Dally, William J., Data-driven charge-pump transmitter for differential signaling.
  2. Poulton, John W.; Greer, III, Thomas Hastings; Dally, William J., Ground referenced single-ended signaling.
  3. Dally, William J., Ground-referenced single-ended memory interconnect.
  4. Dally, William J.; Khailany, Brucek Kurdo; Greer, III, Thomas Hastings; Poulton, John W., Ground-referenced single-ended memory interconnect.
  5. Dally, William J.; Alben, Jonah M.; Poulton, John W.; Greer, III, Thomas Hastings, Ground-referenced single-ended signaling connected graphics processing unit multi-chip module.
  6. Dally, William J.; Alben, Jonah M.; Poulton, John W.; Greer, III, Thomas Hastings, Ground-referenced single-ended signaling connected graphics processing unit multi-chip module.
  7. Dally, William J.; Poulton, John W.; Greer, III, Thomas Hastings; Khailany, Brucek Kurdo; Gray, Carl Thomas, Ground-referenced single-ended system-on-package.
  8. Ahmad, Sagheer; Cumming, Pete; Simeral, Brad; Longnecker, Matthew; Guha, Sudeshna, Low-power states for a computer system with integrated baseband.
  9. de Cesare, Joshua P.; Dalal, Anand, Managing security in a system on a chip (SOC) that powers down a secure processor.
  10. Dally, William J.; Poulton, John W.; Greer, III, Thomas Hastings, Multi-phase ground-referenced single-ended signaling.
  11. Dally, William J.; Khailany, Brucek Kurdo; Poulton, John W.; Greer, III, Thomas Hastings; Gray, Carl Thomas, On-package multiprocessor ground-referenced single-ended interconnect.
  12. Tripathi, Brijesh; Keil, Shane J.; Gulati, Manu; Cho, Jung Wook; Machnicki, Erik P.; Herbeck, Gilbert H.; Millet, Timothy J.; de Cesare, Joshua P.; Dalal, Anand, System on a chip with always-on processor.
  13. Tripathi, Brijesh; Keil, Shane J.; Gulati, Manu; Cho, Jung Wook; Machnicki, Erik P.; Herbeck, Gilbert H.; Millet, Timothy J.; de Cesare, Joshua P.; Dalal, Anand, System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode.
  14. Tripathi, Brijesh; Keil, Shane J.; Gulati, Manu; Cho, Jung Wook; Machnicki, Erik P.; Herbeck, Gilbert H.; Millet, Timothy J.; de Cesare, Joshua P.; Dalal, Anand, System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode.
  15. Dalal, Anand; de Cesare, Joshua P., System on a chip with fast wake from sleep.
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