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Method for strengthening adhesion between dielectric layers formed adjacent to metal layers 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C23C-020/02
  • C23C-020/04
  • H01L-021/28
  • H01L-021/288
출원번호 US-0540036 (2012-07-02)
등록번호 US-8586133 (2013-11-19)
발명자 / 주소
  • Ivanov, Igor C.
  • Zhang, Weiguo
  • Kolics, Artur
출원인 / 주소
  • Lam Research Corporation
대리인 / 주소
    Lettang, Mollie E.
인용정보 피인용 횟수 : 2  인용 특허 : 46

초록

A method is provided which includes forming a metal layer and converting at least a portion of the metal layer to a hydrated metal oxide layer. Another method is provided which includes selectively depositing a dielectric layer upon another dielectric layer and selectively depositing a metal layer a

대표청구항

1. A method for processing a microelectronic topography, comprising: forming a first metal layer upon the microelectronic topography;hydrating at least a portion of the first metal layer to form a hydrated metal oxide layer;depositing a second metal layer upon the hydrated metal oxide layer; anddehy

이 특허에 인용된 특허 (46)

  1. Ivanov, Igor; Zhang, Jonathan Weiguo; Kolics, Artur, Apparatus and method for electroless deposition of materials on semiconductor substrates.
  2. Kaufman Robert ; Downes Gary C. ; Gramarossa Daniel J., Apparatus and method for plating wafers, substrates and other articles.
  3. Fukuzumi, Yoshiaki; Kohyama, Yusuke, Capacitor having a structure capable of restraining deterioration of dielectric film, semiconductor device having the capacitor and method of manufacturing the same.
  4. Kirlin Peter S. ; Van Buskirk Peter C., Chemical mechanical polishing of FeRAM capacitors.
  5. Masaru Watanabe JP, Coating apparatus and coating method.
  6. Zhao Bin ; Vasudev Prahalad K. ; Horwath Ronald S. ; Seidel Thomas E. ; Zeitzoff Peter M., Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer.
  7. Dordi Yezdi ; Malik Muhammad Atif ; Hao Henan ; Franklin Timothy H. ; Stevens Joe ; Olgado Donald, Electro-chemical deposition system.
  8. Dhote Anil M. ; Ramesh Ramamoorthy, Electrode structure for ferroelectric capacitor integrated on silicon.
  9. Shacham-Diamand Yosi ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless deposition equipment or apparatus and method of performing electroless deposition.
  10. Chebiam, Ramanan V.; Dubin, Valery M., Electroless plating bath composition and method of using.
  11. Inoue, Hiroaki; Nakamura, Kenji; Matsumoto, Moriji, Electroless plating liquid and semiconductor device.
  12. Inoue, Hiroaki; Nakamura, Kenji; Matsumoto, Moriji, Electroless plating liquid and semiconductor device.
  13. Stevens, Joseph J.; Lubomirsky, Dmitry; Pancham, Ian; Olgado, Donald J.; Grunes, Howard E.; Mok, Yeuk-Fai Edwin; Dixit, Girish, Electroless plating system.
  14. Graff, Gordon L.; Gross, Mark E.; Affinito, John D.; Shi, Ming-Kun; Hall, Michael G.; Mast, Eric S.; Walty, Robert; Rutherford, Nicole; Burrows, Paul E.; Martin, Peter M., Environmental barrier material for organic light emitting device and method of making.
  15. Pin-Chin C. Wang ; Sergey Lopatin, Formation of alloy material using alternating depositions of alloy doping element and bulk material.
  16. Johnston,Steven W.; Dubin,Valery M.; McSwiney,Michael L.; Moon,Peter, Forming a copper diffusion barrier.
  17. Lopatin, Sergey; Wang, Fei; Schonauer, Diana; Avanzino, Steven C., Interconnect structure formed in porous dielectric material with minimized degradation and electromigration.
  18. Dubin, Valery M.; Thomas, Christopher D.; McGregor, Paul; Datta, Madhav, Interconnect structures and a method of electroless introduction of interconnect structures.
  19. Cahalen John P. ; Sonnenberg Wade, Metallization process and component.
  20. Yoshio, Akira; Segawa, Yuji, Method and apparatus for plating, and plating structure.
  21. Jiang, Tongbi; Li, Li, Method for electroless plating a contact pad.
  22. Sambucetti Carlos Juan ; Rubino Judith Marie ; Edelstein Daniel Charles ; Cabral ; Jr. Cyryl ; Walker George Frederick ; Gaudiello John G ; Wildman Horatio Seymour, Method for forming Co-W-P-Au films.
  23. Lu, Hsin-Hsien; Song, Aaron; Bao, Tien-I; Jang, Syun-Ming, Method for forming a hydrophilic surface on low-k dielectric insulating layers for improved adhesion.
  24. Lee Sang-in,KRX ; Choi Gil-heyun,KRX, Method for forming a wiring layer a semiconductor device.
  25. Chan-Hwa Jung KR; Sung-Min Cho KR; Youn-Jin Oh KR, Method for forming copper interconnections in semiconductor component using electroless plating system.
  26. Jung-Chih Hu TW; Lih-Juann Chen TW, Method for improving the moisture absorption of porous low dielectric film.
  27. Segawa, Yuji; Yoshio, Akira; Suzuki, Masatoshi; Watanabe, Katsumi; Sato, Shuzo, Method of electroless plating and electroless plating apparatus.
  28. Chan Lap ; Li Sam Fong Yau,SGX ; Ng Hou Tee,SGX, Method to encapsulate copper plug for interconnect metallization.
  29. Lim, Victor Seng-Keong; Chooi, Simon; Cha, Randall, Method to fabricate dish-free copper interconnects.
  30. Ivanov, Igor C.; Zhang, Weiguo, Methods and system for processing a microelectronic topography.
  31. Ivanov, Igor C.; Zhang, Welguo, Microelectronic fabrication system components and method for processing a wafer using such components.
  32. Danek Michal ; Levy Karl B., Multilayer diffusion barriers.
  33. Ramanathan, Sivakami; Padhi, Deenesh; Gandikota, Srinivas; Dixit, Girish A., Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application.
  34. Ting Chiu H. ; Holtkamp William H. ; Ko Wen C. ; Lowery Kenneth J. ; Cho Peter, Process chamber and method for depositing and/or removing material on a substrate.
  35. Kuroda,Osamu; Taniyama,Hiroki; Toshima,Takayuki, Processing apparatus and substrate processing method.
  36. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  37. Yang, Kai; Nogami, Takeshi; Brown, Dirk; Pramanick, Shekhar, Self-aligned semiconductor interconnect barrier and manufacturing method therefor.
  38. Sergey D. Lopatin ; Carl J. Galewski, Semiconductor catalytic layer and atomic layer deposition thereof.
  39. Asahina Michio,JPX ; Matsumoto Kazuki,JPX ; Suzuki Eiji,JPX, Semiconductor device and method of fabricating the same.
  40. Nogami, Takeshi; Komai, Naoki; Kito, Hideyuki; Taguchi, Mitsuru, Semiconductor device having a conductive layer with a cobalt tungsten phosphorus coating and a manufacturing method thereof.
  41. Nakano, Hiroshi; Itabashi, Takeyuki; Akahoshi, Haruo, Semiconductor device having cobalt alloy film with boron.
  42. Hideo Takagi JP; Kiyoshi Izumi JP; Wataru Futo JP; Satoshi Otsuka JP; Shigetaka Uji JP; Masataka Hoshino JP; Yukihiro Satoh JP; Koji Endo JP; Yuzuru Ohta JP; Nobuhiro Misawa JP, Semiconductor device with copper wiring and its manufacture method.
  43. Lopatin Sergey D. ; Pramanick Shekhar ; Brown Dirk, Semiconductor metalization barrier.
  44. Nishimura Joichi,JPX ; Morita Akihiko,JPX ; Ohtani Masami,JPX, Substrate cleaning apparatus and method.
  45. Akira Fujisawa JP; Akihito Takano JP; Masayuki Sasaki JP, Thin film capacitance device and printed circuit board.
  46. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.

이 특허를 인용한 특허 (2)

  1. Wirth, Alexandra, Compositions for the currentless deposition of ternary materials for use in the semiconductor industry.
  2. Draeger, Nerissa; Lill, Thorsten; Hymes, Diane, Dielectric repair for emerging memory devices.
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