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A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semi

A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation.

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1. A semiconductor wafer structure for integrated circuit devices, comprising: a bulk substrate;a lower insulating layer formed on the bulk substrate;an electrically conductive back gate layer formed on the lower insulating layer;an upper insulating layer formed on the back gate layer;a hybrid semic

1. A semiconductor wafer structure for integrated circuit devices, comprising: a bulk substrate;a lower insulating layer formed on the bulk substrate;an electrically conductive back gate layer formed on the lower insulating layer;an upper insulating layer formed on the back gate layer;a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation;a plurality of shallow active area level STI recesses formed through the hybrid semiconductor-on-insulator layer; andone or more deep back gate level STI recesses formed through the upper insulating layer and the back gate layer, the one or more deep back gate level STI recesses having portions thereof self-aligned to portions of one or more of the shallow active area level recesses;wherein both the shallow active area STI recesses and the one or more self-aligned deep back gate level STI recesses are filled with one or more insulating materials. 2. The structure of claim 1, wherein the first crystal orientation comprises a (100) crystal orientation and the second crystal orientation comprises a (110) crystal orientation. 3. The structure of claim 1, wherein the first portion of the hybrid semiconductor-on-insulator layer comprises (100) silicon, and the second portion of the hybrid semiconductor-on-insulator layer comprises (110) silicon. 4. The structure of claim 1, wherein the second portion of the hybrid semiconductor-on-insulator layer comprises (100) silicon, and the second portion of the hybrid semiconductor-on-insulator layer comprises one of: (110) silicon germanium and (110) germanium. 5. The structure of claim 1, wherein the upper insulator layer further includes an etch stop layer on the back gate layer. 6. The structure of claim 5, wherein: a bottom surface of the shallow active area level STI recesses stops on an etch stop layer included in the upper insulating layer;a bottom surface of the one or more deep back gate level STI recesses stops on the lower insulating layer;the upper insulator layer further comprises an oxide layer on the etch stop layer; andthe lower insulator layer further comprises an oxide layer, the lower insulator layer corresponding to a lower buried oxide (BOX) layer and the upper insulator layer corresponding to an upper BOX layer. 7. A method of forming a semiconductor wafer structure for integrated circuit devices, the method comprising: forming a first substrate portion, the first substrate portion further comprising a hybrid bulk substrate having a first crystal orientation portion and a second crystal orientation portion, a sacrificial layer formed on the hybrid bulk substrate, a hybrid semiconductor layer formed on the sacrificial layer, a first insulating layer formed on the hybrid semiconductor layer, an electrically conductive layer formed over the first insulating layer, and a second insulating layer, suitable for bonding to another insulating layer, formed on the electrically conductive layer;forming a second substrate portion having a bulk substrate and a third insulating layer formed on the second bulk substrate;bonding the second substrate portion to the first substrate portion so as to define a bonding interface between the second and third insulating layers;separating the resulting bonded structure at a location within the hybrid bulk substrate or the sacrificial layer and removing any remaining portion of the hybrid bulk substrate; andremoving any remaining portion of the sacrificial layer so as to define a hybrid double buried insulator back gate semiconductor-on-insulator wafer structure, wherein the first insulating layer comprises an upper insulating layer, the bonded second and third insulating layers together comprise a lower insulating layer, the hybrid semiconductor layer comprises a hybrid semiconductor-on-insulator layer having the first and second crystal orientation portions, the electrically conductive layer comprises a back gate layer, and the bulk substrate comprises a bulk substrate of the hybrid double buried insulator back gate semiconductor-on-insulator wafer structure. 8. The method of claim 7, wherein the first crystal orientation comprises a (100) crystal orientation and the second crystal orientation comprises a (110) crystal orientation. 9. The method of claim 7, wherein the first portion of the hybrid semiconductor-on-insulator layer comprises (100) silicon, and the second portion of the hybrid semiconductor-on-insulator layer comprises (110) silicon. 10. The structure of claim 7, wherein the first portion of the hybrid semiconductor-on-insulator layer comprises (100) silicon, and the second portion of the hybrid semiconductor-on-insulator layer comprises one of: (110) silicon germanium and (110) germanium. 11. The method of claim 7, wherein the sacrificial layer comprises silicon germanium, the first, second and third insulating layers comprise silicon based oxide layers, bulk substrate comprises silicon, and the hybrid semiconductor layer and hybrid bulk substrate comprise both (100) silicon and (110) silicon portions. 12. The method of claim 7, wherein the electrically conductive layer comprises one or more of: amorphous silicon, undoped polysilicon, doped polysilicon, metal, metal silicide, and metal nitride. 13. The method of claim 7, further comprising performing an annealing procedure to enhance bonding between the second and third insulating layers. 14. The method of claim 7, further comprising forming an etch stop layer between the first insulating layer and the electrically conductive layer. 15. The method of claim 7, further comprising: forming a hardmask layer over the hybrid double buried insulator back gate semiconductor-on-insulator wafer structure;patterning the hardmask layer and etching through the hybrid semiconductor-on-insulator layer so as to form shallow active area level STI recesses;forming a photoresist layer and lithographically patterning the photoresist layer to selectively expose part of one or more of the active area level STI recesses;etching through any remaining portion of the upper insulating layer and the back gate layer, thereby forming one or more deep back gate level STI recesses having portions thereof self-aligned to portions of one or more of the shallow active area level recesses; andfilling both the shallow active area STI recesses and the self-aligned deep back gate level STI recesses with one or more insulating materials, and thereafter planarizing the one or more filled insulating materials;wherein etching of the shallow active area level STI recesses stops on an etch stop layer included in the upper insulating layer, and etching of the deep back gate level STI recess stops on the lower insulating layer. 16. A method of forming a hybrid double buried oxide (BOX), back gate (DBBG) semiconductor-on-insulator (SOI) wafer structure for integrated circuit devices, the method comprising: forming a first substrate portion, the first substrate portion further comprising a hybrid bulk silicon substrate having a (100) crystal orientation portion and a (110) crystal orientation portion, a sacrificial silicon germanium (SiGe) layer epitaxially grown on the hybrid bulk silicon substrate, a hybrid silicon layer grown on the sacrificial layer, the hybrid silicon layer also having a (100) crystal orientation portion and a (110) crystal orientation portion corresponding to the hybrid bulk silicon substrate, a first oxide layer thermally grown or deposited on the hybrid silicon layer, an etch stop layer deposited on the first oxide layer, an electrically conductive back gate layer formed on the etch stop layer, and a second oxide layer thermally grown or deposited on the back gate layer;forming a second substrate portion having a bulk silicon substrate and a third oxide layer thermally grown or deposited on the second bulk substrate;implanting a hydrogen species through the second oxide layer, the electrically conductive back gate layer, the etch stop layer, the first oxide layer and the silicon layer, stopping within or beyond the sacrificial SiGe layer;bonding the second substrate portion to the first substrate portion so as to define a bonding interface between the second and third oxide layers;performing a first annealing procedure to enhance oxide-to-oxide bonding between the second and third oxide layers;performing a second annealing procedure at a higher temperature than the first annealing procedure so as to create a front of connecting voids corresponding to a location of the hydrogen species;separating the bonded structure along the void front; andremoving any remaining part of the hybrid bulk silicon substrate and the sacrificial SiGe layer on the hybrid silicon layer so as to define the hybrid DBBG SOI wafer structure, wherein the first oxide layer and the etch stop layer comprise an upper BOX, the bonded second and third oxide layers together comprise a lower BOX, the hybrid silicon layer comprises a hybrid SOI layer, the back gate layer is disposed between the upper BOX and the lower BOX, and the bulk silicon substrate comprises a bulk substrate of the hybrid DBBG SOI wafer structure. 17. The method of claim 16, further comprising performing a third annealing procedure at a higher temperature than the second annealing procedure to further enhance the oxide-to-oxide bonding between the second and third oxide layers. 18. The method of claim 16, further comprising: forming a hardmask layer over the hybrid DBBG SOI wafer structure;patterning the hardmask layer and etching through the hybrid SOI layer so as to form shallow active area level STI recesses;forming a photoresist layer and lithographically patterning the photoresist layer to selectively expose part of one or more of the active area level STI recesses;etching through any remaining portion of the upper BOX layer and the back gate layer, thereby forming one or more deep back gate level STI recesses having portions thereof self-aligned to portions of one or more of the shallow active area level recesses; andfilling both the shallow active area STI recesses and the self-aligned deep back gate level STI recesses with one or more insulating materials, and thereafter planarizing the one or more filled insulating materials. 19. The method of claim 18, wherein etching of the shallow active area level STI recesses stops on the etch stop layer included in the upper BOX layer. 20. The method of claim 18, wherein etching of the deep back gate level STI recess stops on the lower BOX layer. 21. The method of claim 18, further comprising replacing (110) crystal orientation portions of the hybrid SOI layer with (110) crystal orientation portions of another semiconductor material. 22. The method of claim 21, wherein the another semiconductor material comprises one of silicon germanium and germanium. 23. The method of claim 21, wherein the replacing further comprises: selectively epitaxially growing an initial (110) silicon germanium layer over (110) silicon portions of the hybrid SOI layer; andoxidizing the initial (110) silicon germanium layer so as to cause germanium atoms to be displaced from the initial (110) silicon germanium down into the (110) silicon portions of the hybrid SOI layer, thereby converting the (110) silicon portions of the hybrid SOI layer to (110) silicon germanium and converting the initial (110) silicon germanium layer to a final oxide of silicon layer. 24. The method of claim 23, further comprising removing the final oxide of silicon layer.