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특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Power efficient multiplexer

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H03K-019/094    H03K-019/20   
미국특허분류(USC) 326/113; 326/119; 327/408
출원번호 US-0356396 (2012-01-23)
등록번호 US-8587344 (2013-11-19)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 2  인용 특허 : 139
초록

A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

대표
청구항
▼

1. A circuit comprising: means for outputting at least one bit and a complement of the at least one bit;means for selectively passing one of a plurality of input signals by using the at least one bit and the complement outputted by the means for outputting; andmeans for inverting the one of the plurality of input signals passed by the means for selectively passing, wherein the means for inverting is operable independently of the at least one bit and the complement and a state of a clock signal. 2. The circuit of claim 1, wherein the means for selectively...

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이 특허를 인용한 특허 피인용횟수: 2

  1. Kapoor, Gourav; Agarwal, Preeti; Gupta, Gaurav. Multiplexer circuit. USP2016069366725.
  2. Lewis, David. Tristate multiplexers with immunity to aging effects. USP2018049941882.

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