초록 ▼

An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality of operands from a plurality of operand registers, performs an arithmetic operation on the operands, ob

An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality of operands from a plurality of operand registers, performs an arithmetic operation on the operands, obtains a result of the arithmetic operation and that transmits the result to a result register. The arithmetic logic unit includes a signal propagation path that includes no greater than two routing paths that connect non-immediately adjacent logic elements.

대표청구항 ▼

1. An arithmetic logic unit comprising: a first signal propagation path comprising:a first four input look-up table configured to receive a first one of a plurality of operands; andan adder register that is configured to receive a first output signal from the four input look-up table and coupled to

1. An arithmetic logic unit comprising: a first signal propagation path comprising:a first four input look-up table configured to receive a first one of a plurality of operands; andan adder register that is configured to receive a first output signal from the four input look-up table and coupled to provide a second output signal to a result register; anda second signal propagation path comprising:a carry chain configured to receive an input from a second one of the plurality of operands; anda cascade AND chain configured to receive a third output signal from the carry chain and to provide a fourth output signal to another result register. 2. The arithmetic logic unit of claim 1, wherein the arithmetic logic unit is configured to implement addition functionality. 3. The arithmetic logic unit of claim 1, wherein the arithmetic logic unit is configured to implement subtraction functionality. 4. The arithmetic logic unit of claim 1, wherein the arithmetic logic unit is configured to implement exclusive OR functionality. 5. The arithmetic logic unit of claim 1, wherein the arithmetic logic unit is configured to implement byte rotator functionality. 6. The arithmetic logic unit of claim 1, wherein the arithmetic logic unit is configured to implement barrel shifter functionality. 7. The arithmetic logic unit of claim 1, wherein the carry chain comprises a plurality of logic elements configured to receive the input from the second one of the plurality of operands. 8. A printed circuit board on which is mounted the arithmetic logic unit as defined in claim 1. 9. The printed circuit board defined in claim 8 further comprising: a memory mounted on the printed circuit board and coupled to the arithmetic logic unit. 10. The printed circuit board defined in claim 8 further comprising: processing circuitry mounted on the printed circuit board and coupled to the arithmetic logic unit. 11. The arithmetic logic unit of claim 1, wherein the cascade AND chain comprises a plurality of look-up tables. 12. An arithmetic logic unit comprising: a signal propagation path comprising: at least a first stage implementing a carry chain to reduce routing delays;at least a second stage implementing a cascade AND chain to reduce routing delays, wherein the second stage is coupled to an output signal from the first stage, wherein the cascade AND chain comprises a plurality of look-up tables, and wherein at least one of the look-up tables has an input coupled to the output signal from the first stage and an output coupled to a plurality of cascaded AND gates; andwherein the arithmetic logic unit operates through two non-nearest neighbor routing delays to increase the performance of the arithmetic logic unit. 13. The arithmetic logic unit of claim 12, wherein the arithmetic logic unit is configured to implement addition functionality. 14. The arithmetic logic unit of claim 12, wherein the arithmetic logic unit is configured to implement subtraction functionality. 15. The arithmetic logic unit of claim 12, wherein the arithmetic logic unit is configured to implement exclusive OR functionality. 16. The arithmetic logic unit of claim 12, wherein the arithmetic logic unit is configured to implement byte rotator functionality. 17. The arithmetic logic unit of claim 12, wherein the arithmetic logic unit is configured to implement barrel shifter functionality. 18. A printed circuit board on which is mounted the arithmetic logic unit as defined in claim 12. 19. The printed circuit board defined in claim 18 further comprising: a memory mounted on the printed circuit board and coupled to the arithmetic logic unit. 20. The printed circuit board defined in claim 18 further comprising: processing circuitry mounted on the printed circuit board and coupled to the arithmetic logic unit.