Integrated circuit (IC) chip and method for fabricating the same
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/48
H01L-023/52
출원번호
US-0769735
(2007-06-28)
등록번호
US-8592977
(2013-11-26)
발명자
/ 주소
Chou, Chiu-Ming
Lee, Jin-Yuan
출원인 / 주소
Megit Acquisition Corp.
대리인 / 주소
Seyfarth Shaw LLP
인용정보
피인용 횟수 :
3인용 특허 :
13
초록▼
A method for fabricating an integrated circuit (IC) chip includes providing a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, next forming a first titanium-containing layer over the pad exposed by the opening, next performing a
A method for fabricating an integrated circuit (IC) chip includes providing a passivation layer over a circuit structure, an opening in the passivation layer exposing a pad of the circuit structure, next forming a first titanium-containing layer over the pad exposed by the opening, next performing an annealing process by heating the titanium-containing layer at a temperature of between 300 and 410° C. for a time of between 20 and 150 minutes in a nitrogen ambient with a nitrogen purity of great than 99%, next forming a second titanium-containing layer on the first titanium-containing layer, and then forming a metal layer on the second titanium-containing layer.
대표청구항▼
1. An IC chip comprising: a semiconductor substrate;an aluminum-containing layer coupled to said semiconductor substrate;a first dielectric layer coupled to said semiconductor substrate, wherein a first opening in said first dielectric layer exposes the aluminum-containing layer;a first titanium-con
1. An IC chip comprising: a semiconductor substrate;an aluminum-containing layer coupled to said semiconductor substrate;a first dielectric layer coupled to said semiconductor substrate, wherein a first opening in said first dielectric layer exposes the aluminum-containing layer;a first titanium-containing layer on a first surface of said aluminum-containing layer and a first surface of said first dielectric layer;a second titanium-containing layer on said first titanium-containing layer and directly on the first surface of said first dielectric layer, wherein said second titanium-containing layer is coupled to said first titanium-containing layer and said first surface of said first dielectric layer;a first conductive layer on said second titanium-containing layer; anda polymer layer on a first surface of said first conductive layer. 2. The IC chip of claim 1, wherein said first conductive layer comprises a copper layer on said second titanium-containing layer. 3. The IC chip of claim 1, wherein said first titanium-containing layer comprises a titanium-tungsten alloy. 4. The IC chip of claim 1, wherein said first titanium-containing layer comprises titanium nitride (TiN). 5. The IC chip of claim 1, wherein said second titanium-containing layer comprises a titanium-tungsten alloy. 6. The IC chip of claim 1, wherein said first titanium-containing layer has a thickness between 0.01 and 0.7 micrometers. 7. The IC chip of claim 1, wherein said second titanium-containing layer has a thickness between 0.02 and 0.5 micrometers. 8. The IC chip of claim 1, wherein said first conductive layer comprises a gold layer on said second titanium-containing layer. 9. The IC chip of claim 1, wherein said first dielectric layer comprises a polymer. 10. The IC chip of claim 1 further comprising a second conductive layer over said semiconductor substrate, wherein said second conductive layer comprises a copper layer and a third conductive layer at a bottom and a sidewall of said copper layer, wherein said aluminum-containing layer is further over said second conductive layer. 11. The IC chip of claim 10 further comprising a second dielectric layer over said semiconductor substrate, wherein said second dielectric layer comprises an oxide, wherein a second opening in said second dielectric layer is over a contact point of said second conductive layer, and said contact point is at a bottom of said second opening, wherein said aluminum-containing layer is further over said contact point and said second dielectric layer and coupled to said contact point through said second opening. 12. An IC chip comprising: a semiconductor substrate;a conductive pad on a surface of the semiconductor substrate;a first conductive layer on said conductive pad, wherein said first conductive layer comprises a first titanium-containing layer and an aluminum-containing layer on said first titanium-containing layer;a polymer layer over said semiconductor substrate, wherein a first opening in said polymer layer is over said first conductive layer;a second titanium-containing layer on a first surface of said first conductive layer opposite the conductive pad;a second metal conductive layer on said second titanium-containing layer and a first surface of said polymer layer opposite the semiconductor substrate, wherein said second conductive layer is directly on said second titanium-containing layer and said first surface of said polymer layer; anda third conductive layer on said second conductive layer. 13. The IC chip of claim 12, wherein said third conductive layer comprises a copper layer on said second conductive layer. 14. The IC chip of claim 12, wherein said first titanium-containing layer comprises a titanium-tungsten alloy. 15. The IC chip of claim 12, wherein said first titanium-containing layer comprises titanium nitride (TiN). 16. The IC chip of claim 12, wherein said second titanium-containing layer comprises a titanium-tungsten alloy. 17. The IC chip of claim 12, wherein said first titanium-containing layer has a thickness between 0.01 and 0.5 micrometers. 18. The integrated circuit of claim 12, wherein said second titanium-containing layer has a thickness between 0.01 and 0.7 micrometers. 19. The IC chip of claim 12, wherein said third conductive layer comprises a gold layer on said second conductive layer. 20. The IC chip of claim 12, wherein said second conductive layer comprises titanium. 21. The IC chip of claim 12 further comprising a fourth conductive layer over said semiconductor substrate, wherein said fourth conductive layer comprises a copper layer, and a fifth conductive layer at a bottom and a sidewall of said copper layer, wherein said forth conductive layer is further over said fifth conductive layer. 22. The IC chip of claim 21 further comprising a dielectric layer over said semiconductor substrate, wherein said dielectric layer comprises an oxide, wherein a second opening in said dielectric layer is over a contact point of said fourth conductive layer, and said contact point is at a bottom of said second opening, wherein said first conductive layer is further on said contact point and said dielectric layer and coupled to said contact point through said second opening.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (13)
Hua,Fay; Wu,Albert T.; Jeng,Kevin; Seshan,Krishna, Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same.
Kim Nam Seog,KRX ; Jang Dong Hyeon,KRX ; Kang Sa Yoon,KRX ; Kwon Heung Kyu,KRX, Chip scale packages and methods for manufacturing the chip scale packages at wafer level.
Braeckelmann Gregor ; Venkatraman Ramnath ; Herrick Matthew Thomas ; Simpson Cindy R. ; Fiordalice Robert W. ; Denning Dean J. ; Jain Ajay ; Capasso Cristiano, Method for forming a semiconductor device.
Sakurai, Kazunori; Ota, Tsutomu; Matsushima, Fumiaki; Makabe, Akira, Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic device.
Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.
Schneegans, Manfred; Haering, Franziska; Schulze, Hans-Joachim; Weidgans, Bernhard, Semiconductor device with metal structure electrically connected to a conductive structure.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.