IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
|
출원번호 |
US-0194723
(2011-07-29)
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등록번호 |
US-8599523
(2013-12-03)
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발명자
/ 주소 |
- Ostrovsky, Michael
- Libretto, John
- Jansen, Ronald
- Kamor, Michael
- Kevelos, Adam
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출원인 / 주소 |
- Leviton Manufacturing Company, Inc.
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
11 인용 특허 :
149 |
초록
▼
An arc fault circuit interrupter is disclosed. This arc fault circuit interrupter can include any one or more of three different sensors such as a high frequency sensor, and any one of lower frequency sensors such as a current sensor or a differential sensor. The arc fault circuit interrupter can be
An arc fault circuit interrupter is disclosed. This arc fault circuit interrupter can include any one or more of three different sensors such as a high frequency sensor, and any one of lower frequency sensors such as a current sensor or a differential sensor. The arc fault circuit interrupter can be configured as an in line arc fault circuit interrupter installed in a wall box. In addition, the arc fault circuit interrupter can include a processor configured to determine any one of a series arc fault, or a parallel arc fault.
대표청구항
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1. A circuit interrupter device comprising: a device current path comprising: a phase conductive path having a line side and a load side;a neutral conductive path having a line side and a load side;a differential sensor, communicatively arranged and configured to read a current differential between
1. A circuit interrupter device comprising: a device current path comprising: a phase conductive path having a line side and a load side;a neutral conductive path having a line side and a load side;a differential sensor, communicatively arranged and configured to read a current differential between the phase and neutral conductive paths and to output a differential sensor signal representative of a value of the current differential;a high frequency sensor communicatively arranged and configured to read a high frequency signal along one of the phase and neutral conductive paths and to output a high frequency sensor signal representative of a presence of the high frequency signal;a current sensor communicatively arranged and configured to read a current level along one of the phase and neutral conductive paths and to output a current level sensor signal representative of a value of the current level; anda processor configured to:(i) receive the differential sensor signal, the high frequency sensor signal, and the current level sensor signal,(ii) increment a count in a counter based on at least in part on the high frequency sensor signal, and(iii) detect a presence of an arc fault condition based on the count in the counter. 2. The device as in claim 1, wherein the high frequency sensor comprises a high frequency coil having a core, the core being selected from the group consisting of: an air core, a polymeric core, a ferrous core, and a high permeability magnetic core. 3. The device as in claim 1, wherein the current sensor is selected from the group consisting of: a current transformer, a hall-effect sensor, and a shunt. 4. The device of claim 1, further comprising a voltage sensor configured to output a voltage sensor signal indicative of a voltage between the phase and neutral conductive paths. 5. The device as in claim 1, wherein said high frequency sensor comprises a high permeability magnetic core. 6. The device as in claim 1, further comprising an interrupter circuit configured to interrupt at least one of said phase and neutral conductive paths upon the detection of an arc fault by said processor. 7. The device as in claim 1, further comprising an indicator, wherein said indicator is in communication with said processor and is configured to provide indication of a presence of an arc fault. 8. The device as in claim 1, further comprising at least one voltage level measurement circuit having an output coupled to said processor. 9. The device as in claim 1, further comprising at least one voltage regulator which is configured to provide power to said at least one processor. 10. The device as in claim 1, wherein at least one of said high frequency sensor, said differential sensor and said current sensor is positioned in a nested configuration with another sensor. 11. The device as in claim 1, wherein the processor further comprises: a clock to indicate a length of a predetermined measurement period;a comparator, operably coupled to the counter, to compare the count in the counter to a predetermined value over the predetermined measurement period, andwherein the processor is configured to reset the counter at the end of the predetermined measurement period. 12. The device as in claim 1, wherein the processor is configured to detect the presence of the arc fault condition based on a number of predetermined measurement periods in which the count exceeds the predetermined value. 13. A circuit interrupter device comprising: a device current path comprising: a phase conductive path having a line side and a load side;a neutral conductive path having a line side and a load side;a high frequency sensor, communicatively arranged and configured to read an electrical signal along a phase conductive path and along a neutral conductive path and to output a high frequency sensor signal indicative of a frequency range of the electrical signal on the phase and neutral conductive paths;a processor configured to receive the high frequency sensor signal, wherein the processor is configured to detect a presence of an arc fault based on the high frequency sensor signal; andan interrupter circuit configured to interrupt at least one of the phase and neutral conductive paths in response to detection of the arc fault by the processor. 14. The device as in claim 13, further comprising a differential sensor configured to output a power line differential signal indicative of a power line current differential between the phase and neutral conductive paths. 15. The device as in claim 13, further comprising a current sensor communicatively coupled to at least one of the phase and neutral conductive paths, wherein the current sensor is configured to generate a current level signal indicative of a current level in at least one of the phase and neutral conductive paths. 16. The device as in claim 15, wherein, responsive to the detection of the arc fault by the processor, if the current level in said at least one of the phase and neutral conductive paths is zero, the interrupter circuit is configured not to interrupt at least one of the phase and neutral conductive paths. 17. The device as in claim 13, wherein said phase conductive path and said neutral conductive path are arranged such that said high frequency sensor is configured to read a current of said phase conductive path as a same polarity as a current of said neutral conductive path. 18. The device as in claim 13, wherein said phase conductive path and said neutral conductive path are arranged such that said high frequency sensor is configured to read a current of said phase conductive path as an opposite polarity as a current of said neutral conductive path. 19. The device of claim 13, further comprising an indicator wherein said indicator is configured to provide an indication of the presence of an arc fault. 20. The device as in claim 13, wherein the high frequency sensor comprises a high frequency coil having a core, the core being selected from the group consisting of: an air core, a polymeric core, a ferrous core, and a high permeability magnetic core. 21. The device as in claim 15, wherein the current sensor is selected from the group consisting of: a current transformer, a hall-effect sensor, and a shunt. 22. The device as in claim 13, wherein said high frequency sensor is configured such that a current differential between the phase and neutral conductive paths is not capable of saturating the high frequency sensor. 23. The device as in claim 13, wherein the processor is further configured to: i) increment a first count in a first counter in response to an indication that the frequency range is within first predetermined frequency range;ii) increment a second count in a second counter in response to an indication that the frequency range is within second predetermined frequency range; andiii) determine the presence of an arc by comparing the first number and the second number to at least one predetermined value. 24. A process for determining a series arc comprising: a) setting a first time period;b) setting a second time period which is a fraction of said first time period;c) monitoring a frequency and a current of a signal on an electrical line;d) counting a number of second time periods that the frequency is within a first predetermined frequency range to find a first number;e) counting a number of second time periods that the frequency is within a second predetermined frequency range to find a second number; andf) determining a presence of an arc by comparing said first number and said second number to at least one predetermined value. 25. The process as in claim 24, wherein f) comprises: i) finding a third number by subtracting said first number from said second number; andii) comparing said third number to said at least one predetermined value. 26. The process as in claim 24, wherein said first predetermined frequency range is from 2 MHz to below 4 MHz. 27. The process as in claim 24, wherein said second predetermined frequency range is at least 4 MHz to a higher value. 28. The process as in claim 27, wherein said second predetermined frequency range is from at least 4 MHz to 10 MHz. 29. The process as in claim 24, further comprising: determining an average current for each of said second time periods;determining a peak current for said first time period based on the average currents for each of said second time periods; anddetermining a third time period comprising a plurality of said first time periods, based upon said peak current. 30. The process as in claim 29, wherein said first time period is a processor half cycle. 31. The process as in claim 29, wherein said second time period is 250 microseconds. 32. The process as in claim 29, wherein determining a third time period comprises: determining a third time period to be 1 second if said current reading is below 10 A;determining a third time period to be 400 milliseconds if said current is above 10 A but below 20 A;determining a third time period to be 200 milliseconds if said current is above 20 A but below 30 A; anddetermining a third time period to be 100 milliseconds if said current is above 30 A. 33. The process as in claim 32, wherein f) further comprises: determining a bit identity comprising at least one of an arcing bit or an non-arcing bit for each of said first time periods,inserting said bit identity into a shift register, andcomparing a number of arcing bits to a predetermined number for said third time period. 34. A process for determining a presence of a parallel arc, the process comprising: a) starting a processor time clock for a series of first predetermined time periods;b) monitoring at least a current and a frequency on a line;c) determining whether a peak current on the line is greater than a predetermined peak current value;d) determining the presence of arcing noise on the line based upon at least one predetermined frequency value for at least one first predetermined time period in said series of first predetermined time periods;e) starting at least one counter to record the presence of at least one arcing characteristic for the at least one first predetermined time period of said series of first predetermined time periods within a second predetermined time period;f) comparing a count provided by said at least one counter recording a presence of said at least one arcing characteristic for said first predetermined time period across said second predetermined time period to find a first number; andg) determining the presence of the parallel arc by comparing said first number to a predetermined value. 35. The process as in claim 34, wherein said first predetermined time period is a processor half cycle. 36. The process as in claim 34, wherein said first predetermined time period is a fraction of a processor half cycle. 37. The process as in claim 34, wherein said step of determining a peak current value comprises determining whether said peak current is above 24 A. 38. The process as in claim 34, wherein said step of starting at least one counter comprises starting at least one of the following counters: a parallel arc interval counter; a current break counter; a current rise counter; a noise counter. 39. The process as in claim 38, wherein said parallel arc interval counter is incremented by determining the presence of the peak current and determining a number of occurrences of at least one of a high frequency noise or a low frequency noise. 40. The process as in claim 39, wherein said low frequency noise is a noise reading of frequency above a first predetermined frequency value and at or below a second predetermined frequency value, and said high frequency noise is a noise reading above said second frequency value. 41. The process as in claim 38, wherein said current break counter is incremented when said parallel arc counter has incremented and an average current is below a predetermined average current value or the peak current is below the predetermined peak current value. 42. The process as in claim 38, wherein said current rise counter is incremented when it determines that a difference in a measured rectified current between two successive first predetermined time periods is greater than a predetermined value. 43. The process as in claim 38, wherein said noise counter is incremented when it determines that a difference between a number of occurrences of frequency above a first predetermined frequency for each first predetermined time period is greater than a number of occurrences of a frequency below said first predetermined frequency for each first predetermined time period across said second predetermined time period. 44. The process as in claim 34, further comprising recording a voltage drop during at least one of said first predetermined time periods. 45. The process as in claim 34, further comprising setting the second predetermined time period based upon a peak current reading in at least one of said first predetermined time periods. 46. A process for determining a presence of a parallel to ground arcing condition, the method comprising: a) starting a processor time clock for a series of first and second predetermined time periods;b) reading a differential current from a differential core;c) determining whether the differential current is above a predetermined value;d) starting a timer in response to a determination in c) that the differential current is above the predetermined value;e) recording for the first predetermined time period that the differential current is above the predetermined value;f) recording for the second predetermined time period that the differential current is above the predetermined value; andg) determining the presence of the parallel to ground arcing condition based at least in part on the recordings in e) and f).
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