A processor framework includes a compiler to add control information to an instruction sequence at compile time. The control information is added in the instruction sequence prior to a control-flow changing instruction. Microarchitecture is configured to use the control information at runtime to pre
A processor framework includes a compiler to add control information to an instruction sequence at compile time. The control information is added in the instruction sequence prior to a control-flow changing instruction. Microarchitecture is configured to use the control information at runtime to predict an outcome of the control-flow changing instruction prior to fetching the control-flow changing instruction.
대표청구항▼
1. A method for use with a processor, comprising: adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of
1. A method for use with a processor, comprising: adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime;removing the control-flow changing instruction from the instruction sequence; andin hardware, using the control information at runtime (i) to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and (ii) to fetch an instruction corresponding to the path. 2. The method of claim 1, wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency and processor energy consumption. 3. The method of claim 1, wherein the control information comprises part of a payload of a coprocessor instruction. 4. The method of claim 1, wherein the control information is removed from the instruction sequence at runtime before entering a pipeline of the processor; wherein the outcome of the control-flow changing instruction is predicted prior to the control-flow changing instruction entering the pipeline. 5. The method of claim 1, wherein the control information comprises code for selecting a dynamic branch prediction mechanism at runtime. 6. The method of claim 1, further comprising adding control information to the instruction sequence to stall fetching until a second control-flow changing instruction is executed that is not predictable statically or dynamically. 7. The method of claim 1, wherein the control information comprises static information that suggests one or more of plural dynamic prediction mechanisms. 8. The method of claim 1, further comprising: performing an analysis of the instruction sequence at compile time in order to generate the control information. 9. The method of claim 1, wherein the control information identifies a position of the control-flow changing instruction in the instruction sequence. 10. The method of claim 1, wherein the outcome of the control-flow changing instruction is coded in the control information. 11. The method of claim 1, wherein the control information specifies a condition under which a control-flow change at an end of the instruction sequence should occur. 12. A system for use with a processor, comprising: a machine to execute a compiler (i) to add control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime, and (ii) to remove the control-flow changing instruction from the instruction sequence; andmicroarchitecture to use the control information at runtime to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and (ii) to fetch an instruction corresponding to the path, the microarchitecture comprising hardware. 13. The system of claim 12, wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency and processor energy consumption. 14. The system of claim 12, wherein the control information comprises part of a payload of a coprocessor instruction. 15. The system of claim 12, wherein the microarchitecture is configured to remove the control information from the instruction sequence at runtime before entering a pipeline of the processor; and wherein the outcome of the control-flow changing instruction is predicted prior to the control-flow changing instruction entering the pipeline. 16. The system of claim 12, wherein the control information comprises code for selecting a dynamic branch prediction mechanism at runtime. 17. The system of claim 12, wherein the compiler is configured to add control information to the instruction sequence to stall fetching until a second control-flow changing instruction is executed that is not predictable statically or dynamically. 18. The system of claim 12, wherein the control information comprises static information that suggests one or more of plural dynamic prediction mechanisms. 19. The system of claim 12, wherein the compiler is configured to perform an analysis of the instruction sequence at compile time in order to generate the control information. 20. The system of claim 12, wherein the control information identifies a position of the control-flow changing instruction in the instruction sequence. 21. The system of claim 12, wherein the outcome of the control-flow changing instruction is coded in the control information. 22. The system of claim 12, wherein the control information specifies a condition under which a control-flow change at an end of the instruction sequence should occur. 23. A method for use with a processor, comprising: adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction;extracting the control information from a buffer prior to the control information entering a pipeline of the processor; andin hardware, using the control information at runtime (i) to predict an outcome of the control-flow changing instruction prior to fetching the control-flow changing instruction, the outcome comprising a path following the control-flow changing instruction, (ii) to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path, and (iii) to generate control signals for use during execution of the instruction corresponding to the path predicted by the control information. 24. The method of claim 23, wherein the control information comprises an instruction that is used to enhance different types of operation of the processor. 25. The method of claim 24, wherein the different types of operation comprise power and performance. 26. The method of claim 25, wherein the control information is usable to select between different types of branch prediction. 27. A system for use with a processor, comprising: a machine to execute a compiler to add control information to an instruction sequence at compile time, the compiler for adding the control information in the instruction sequence prior to a control-flow changing instruction; andmicroarchitecture: (i) to extract the control information from a buffer prior to the control information entering a pipeline of the processor, and(ii) to use the control information at runtime: (a) to predict an outcome of the control-flow changing instruction prior to fetching the control-flow changing instruction, the outcome comprising a path following the control-flow changing instruction,(b) to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path; and(c) to generate control signals for use during execution of the instruction corresponding to the path predicted by the control information;wherein the microarchitecture comprises hardware. 28. The system of claim 27, wherein the control information comprises an instruction that is used to enhance different types of operation of the processor. 29. The system of claim 28, wherein the different types of operation comprise power and performance. 30. The system of claim 27, wherein the control information is usable to select between different types of branch prediction. 31. A method for use with a processor, comprising: adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction; andin hardware, using the control information at runtime (i) to predict an outcome of the control-flow changing instruction, the outcome being predicted without requiring fetching of the control-flow changing instruction, the outcome comprising a path following the control-flow changing instruction, (ii) to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path, and (iii) to generate control signals for use during execution of the instruction corresponding to the path predicted by the control information. 32. The method of claim 31, wherein the control information comprises static information. 33. The method of claim 31, wherein the control information comprises an instruction that is used to enhance different types of operation of the processor. 34. The method of claim 33, wherein the different types of operation comprise power and performance. 35. The method of claim 31, wherein the control information is usable to select between different types of branch prediction systems. 36. The method of claim 31, wherein the control-flow changing instruction comprises a branch instruction; and wherein predicting the outcome comprises resolving the branch instruction. 37. The method of claim 31, further comprising: performing an analysis of the instruction sequence at compile time in order to generate the control information. 38. The method of claim 31, wherein the control information identifies a position of the control-flow changing instruction in the instruction sequence. 39. A system for use with a processor, comprising: a machine to execute a compiler to add control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction; anda microarchitecture to use the control information at runtime (i) to predict an outcome of the control-flow changing instruction, the outcome being predicted without requiring fetching of the control-flow changing instruction, the outcome comprising a path following the control-flow changing instruction, (ii) to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path, the microarchitecture comprising hardware, and (iii) to generate control signals for use during execution of the instruction corresponding to the path predicted by the control information. 40. The system of claim 39, wherein the control information comprises static information. 41. The system of claim 39, wherein the control information comprises an instruction that is used to enhance different types of operation of the processor. 42. The system of claim 41 wherein the different types of operation comprise power and performance. 43. The system of claim 39, wherein the control information is usable to select between different types of branch prediction systems. 44. The system of claim 39, wherein the control-flow changing instruction comprises a branch instruction; and wherein predicting the outcome comprises resolving the branch instruction. 45. The system of claim 39, wherein the compiler is configured to perform an analysis of the instruction sequence at compile time in order to generate the control information. 46. The system of claim 39, wherein the control information identifies a position of the control-flow changing instruction in the instruction sequence. 47. A method for use with a processor, comprising: adding control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime, and compile-time comprising a time during which program code is translated into the instruction sequence;at compile-time, removing the control-flow changing instruction from the instruction sequence; andin hardware, using the control information at runtime to predict an outcome of the control-flow changing instruction that was removed at compile-time, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction. 48. The method of claim 47, further comprising determining, without decoding the control-flow changing instruction, from where to fetch an instruction corresponding to the path. 49. A system for use with a processor, comprising: a machine to execute a compiler (i) to add control information to an instruction sequence at compile time, the control information being added in the instruction sequence prior to a control-flow changing instruction, the control-flow changing instruction for changing a control flow of a computer program at runtime, and compile-time comprising a time during which program code is translated into the instruction sequence, and (ii) to remove the control-flow changing instruction from the instruction sequence at compile time; andmicroarchitecture to use the control information at runtime to predict an outcome of the control-flow changing instruction that was removed at compile-time, the microarchitecture comprising hardware, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction. 50. The system of claim 49, wherein the microarchitecture is configured to use the control information at runtime to fetch, without decoding the control-flow changing instruction, an instruction corresponding to the path.
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