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Scheduling multithreaded programming instructions based on dependency graph 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0582204 (2006-01-26)
등록번호 US-8612957 (2013-12-17)
국제출원번호 PCT/CN2006/000162 (2006-01-26)
§371/§102 date 20060608 (20060608)
국제공개번호 WO2007/085121 (2007-08-02)
발명자 / 주소
  • Guo, Xiaofeng
  • Dai, Jinquan
  • Li, Long
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Trop, Pruner & Hu, P.C.
인용정보 피인용 횟수 : 0  인용 특허 : 26

초록

A computer implemented method for scheduling multithreaded programming instructions based on the dependency graph wherein the dependency graph organizes the programming instruction logically based on blocks, nodes, and super blocks and wherein the programming instructions could be executed outside o

대표청구항

1. A computer implemented method for rearranging a computer program comprising: organizing the computer program logically into a plurality of blocks;constructing a dependency graph based on the organization of the plurality of blocks in the computer program;determining a critical section included in

이 특허에 인용된 특허 (26)

  1. Heishi,Taketo; Ogawa,Hajime; Tani,Takenobu; Sasagawa,Yukihiro, Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions.
  2. Odani Kensuke,JPX ; Tanaka Akira,JPX ; Tanaka Hirohisa,JPX, Compiler for optimizing memory instruction sequences by marking instructions not having multiple memory address paths.
  3. Iwata Yasushi,JPX ; Asato Akira,JPX, Compiling apparatus and method for a VLIW system computer and a recording medium for storing compile execution programs.
  4. Ishizaki,Kauaki; Inagaki,Tatshushi; Komatsu,Hideaki, Compiling method, apparatus, and program.
  5. Mitran, Marcel; Vasilevskiy, Alexander, Configuring a dependency graph for dynamic by-pass instruction scheduling.
  6. Franssen Frank,BEX ; van Swaaij Michael,BEX ; Nachtergaele Lode,BEX ; Samsom Hans,BEX ; Catthoor Francky,BEX ; De Man Hugo,BEX, Control flow and memory management optimization.
  7. Ogawa, Hajime; Odani, Kensuke, Instruction string optimization with estimation of basic block dependence relations where the first step is to remove self-dependent branching.
  8. Roediger Robert Ralph ; Schmidt William Jon, Lifetime-sensitive instruction scheduling mechanism and method.
  9. Archambault, Roch Georges; Blainey, Robert James, Loop allocation for optimizing compilers.
  10. Tarsy Gregory (Scotts Valley CA) Woodard Michael J. (Fremont CA), Method and apparatus for cost-based heuristic instruction scheduling.
  11. Lauterbach Gary R., Method and apparatus for designing a circuit by analyzing selected artificial hardware dependencies inserted into a dyn.
  12. Li, Long; Dai, Jinquan; Guo, Xiaofeng, Method and apparatus for ordering code based on critical sections.
  13. Bardasz Theodore (49 Parkerville Rd. Chelmsford MA 01824) Malnati Stefano (148 Main St. ; Unit B533 N. Andover MA 01845), Method and apparatus for representing data dependencies in software modeling systems.
  14. Subramanian Krishna ; Baylin Boris, Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler.
  15. Gupta Rajiv (Ossining NY) Chi Chi-Hung (Croton-on-Hudson NY), Method for compiling computer instructions for increasing instruction cache efficiency.
  16. Cramer Timothy J. (Pleasanton CA) Cox David M. (Livermore CA), Method for representing scalar data dependences for an optimizing compiler.
  17. Wu,Youfeng, Methods and apparatus to compile a software program to manage parallel μcaches.
  18. Archambault Roch G.,CAX, Optimizing compilation of pointer variables in the presence of indirect function calls.
  19. McKinsey, Chris M.; Bharadwaj, Jayashankar, Path speculating instruction scheduler.
  20. Heishi, Taketo; Odani, Kensuke, Processor, compiling apparatus, and compile program recorded on a recording medium.
  21. Nair, Sreekumar Ramakrishnan; Damron, Peter C., Region based optimizations using data dependence graphs.
  22. Muthukumar, Kalyan; Lavery, Daniel M.; Hoflehner, Gerolf F.; Lim, Chu cheow; Collard, Jean Francois, Resource-aware scheduling for compilers.
  23. Damron, Peter C.; Kosche, Nicolai, System and method for scheduling instructions to maximize outstanding prefetches and loads.
  24. Chan Sun C. (Fremont CA) Dehnert James C. (Palo Alto CA) Lo Raymond W. (Sunnyvale CA) Towle Ross A. (San Francisco CA), System and method of generating object code using aggregate instruction movement.
  25. Simons Barbara Bluestein ; Sarkar Vivek, System, method, and program product for loop instruction scheduling hardware lookahead.
  26. Babb, II, Robert G.; Parry, Michael H.; Byassee, Jason S.; Meyers, Ted L.; Mooney, David R., Systems and methods for identifying and displaying dependencies.
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