A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the
A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.
대표청구항▼
1. A reference current source circuit comprising: a first current mirror circuit for generating a plurality of first minute currents from a power supply voltage, the plurality of first minute currents corresponding to each other;a MOS transistor having a gate, a drain and a source, and generating an
1. A reference current source circuit comprising: a first current mirror circuit for generating a plurality of first minute currents from a power supply voltage, the plurality of first minute currents corresponding to each other;a MOS transistor having a gate, a drain and a source, and generating an output current based on a voltage induced across the drain and the source;a gate bias voltage generator circuit comprising a plurality of first MOS transistors operating in a subthreshold saturation region based on a plurality of first minute currents selected from the plurality of first minute currents, generating a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region based on selected first minute currents, and applying the gate bias voltage to the gate of the MOS transistor;a drain bias voltage generator circuit comprising a plurality of second MOS transistors operating in the subthreshold saturation region based on a plurality of first minute currents selected from the plurality of first minute currents, generating a drain bias voltage based on selected first minute currents, and applying the drain bias voltage to the drain of the MOS transistor; andan added bias voltage generator circuit for generating an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, based on one first minute current selected from the plurality of first minute currents, so that the output current becomes constant against temperature changes,wherein the drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of adding results to the drain of the MOS transistor as the drain bias voltage. 2. The reference current source circuit as claimed in claim 1, wherein the added bias voltage generator circuit comprises a MOS transistor ladder circuit,wherein the MOS transistor ladder circuit comprises:a first nMOS transistor which is diode-connected and operates in the subthreshold saturation region based on the one first minute current; anda second nMOS transistor, which is connected in series to the first nMOS transistor via a connection point and operates in a subthreshold linear region based on the one first minute current, andwherein the MOS transistor ladder circuit outputs a voltage generated at the connection point as the added bias voltage. 3. The reference current source circuit as claimed in claim 2, wherein the first nMOS transistor is selected from the plurality of second MOS transistors. 4. The reference current source circuit as claimed in claim 1, wherein the added bias voltage generator circuit comprises a MOS transistor ladder circuit,wherein the MOS transistor ladder circuit comprises:a first nMOS transistor which is diode-connected and operates in the subthreshold saturation region based on the one first minute current; anda plurality of second nMOS transistors, which are connected in series to the first nMOS transistor via a first connection point, operate in a subthreshold linear region based on the one first minute current, and are connected in series with each other via at least one second connection point, andwherein the MOS transistor ladder circuit outputs a voltage generated at one of the first connection point and the at least one second connection point as the added bias voltage. 5. The reference current source circuit as claimed in claim 4, wherein the first nMOS transistor is selected from the plurality of second MOS transistors. 6. The reference current source circuit as claimed in claim 5, wherein the plurality of second nMOS transistors are connected between the first connection point and a ground,wherein the added bias voltage generator circuit further comprises a plurality of switches connected between the first connection point and the ground, and between each of the at least one second connection point and the ground, respectively, andwherein one of the plurality of switches is controlled to be turned on. 7. The reference current source circuit as claimed in claim 4, wherein the plurality of second nMOS transistors are connected between the first connection point and a ground,wherein the added bias voltage generator circuit further comprises a plurality of switches connected between the first connection point and the ground, and between each of the at least one second connection point and the ground, respectively, andwherein one of the plurality of switches is controlled to be turned on. 8. The reference current source circuit as claimed in claim 1, wherein the first current mirror circuit includes a plurality of cascode current mirror circuits. 9. The reference current source circuit as claimed in claim 1, further comprising a startup circuit, wherein the startup circuit comprises:a detector circuit for detecting a non-operating time of the reference current source circuit; anda startup transistor circuit for starting up the reference current source circuit by flowing a predetermined startup current through the reference current source circuit when the non-operating time of the reference current source circuit is detected by the detector circuit. 10. The reference current source circuit as claimed in claim 9, wherein the startup circuit further comprises a current supply circuit for supplying a bias operating current to the detector circuit, andwherein the current supply circuit comprises:a third minute current generator circuit for generating a predetermined second minute current from the power supply voltage; anda second current mirror circuit for generating a third minute current corresponding to the second minute current as the bias operating current.
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이 특허에 인용된 특허 (5)
Digele Georg,DEX, Electronic circuit with partitioned power transistor.
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