[특허]Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set

Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-017/50 G06F-019/00 G06F-013/10 G06F-015/177 G06F-015/78
출원번호	US-0860829 (2010-08-20)
등록번호	US-8621410 (2013-12-31)
발명자 / 주소	Willis, John C.
출원인 / 주소	FTL Systems, Inc.
대리인 / 주소	Ojanen, Karuna
인용정보	피인용 횟수 : 0 인용 특허 : 25

초록 ▼

An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays.

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1. A method of computer processing comprising: supplying source code to a computer having at least one processor having a first instruction set and at least one dynamically reconfigurable logic array;analyzing the source code to identify one or more processor states;binding the one or more processor states to one or more technology types and subtypes;synthesizing logic to reconfigure the at least one dynamically reconfigurable logic array to execute the processor states;reconfiguring the at least one dynamically reconfigurable logic array to a specific set of cell designs and routing options to implement the one or more technology types and subtypes;executing the one or more processor states on the at least one processor and on the at least one reconfigured logic array;wherein the one or more processor states executing on the reconfigured logic array are different than the one or more processor states executing on the at least one processing processor having the first instruction set. 2. The method of claim 1 wherein the first instruction set is a fixed instruction set. 3. The method of claim 1 wherein the one or more technology types are stored in a library. 4. The method of claim 1 wherein the one or more technology types or subtypes are supplied by source code. 5. The method of claim 1, wherein the one or more technology types or subtypes are optimized for one or more processor states. 6. The method of claim 1, wherein the at least one dynamically reconfigurable logic array is reconfigured to comprise at least one of the following: one or more integer processing units;one or more floating point processing units;one or more bit processing units;one or more image processing units;one or more vector processing units;one or more mixed-signal/analog/RF/MW signal processing units. 7. A method of computer processing comprising: supplying source code to a computer having at least one processor having a fixed first instruction set and at least one dynamically reconfigurable logic array, the at least one dynamically reconfigurable logic array not implemented on a same integrated circuit as the at least one processor;analyzing the source code to identify one or more processor states;binding the one or more processor states to one or more technology types and subtypes not embedded in the source code;synthesizing logic to reconfigure the at least one dynamically reconfigurable logic array to execute the processor states;reconfiguring the at least one dynamically reconfigurable logic array to a specific set of cell designs and routing options to implement addition of one or technology types and subtypes;executing the one or more processor states on the at least one processor and on the at least one reconfigured logic array;wherein the one or more processor states executing on the reconfigured logic array are different than the one or more processor states executing on the at least one processor having the fixed first instruction set;wherein executing the one or more processor states on the reconfigured logic array does not require determining on an instruction-by-instruction basis whether the reconfigured logic array is configured with one or more technology types to execute the one or more processor states on the reconfigured logic array; andwherein the at least one processor is not designed to natively offload said one or more processor states executing on the at least one processor to the reconfigured logic array. 8. The method of claim 7 wherein the one or more technology types are stored in a library. 9. The method of claim 7 wherein the one or more technology types or subtypes are supplied by the source code. 10. The method of claim 7, wherein the one or more technology types or subtypes are optimized for one or more processor states. 11. The method of claim 7, wherein the at least one dynamically reconfigurable logic array is reconfigured to comprise at least one of the following: one or more integer processing units;one or more floating point processing units;one or more bit processing units;one or more image processing units;one or more vector processing units;one or more mixed-signal/analog/RF/MW signal processing units. 12. The method of claim 7 wherein the first instruction set is an x86 instruction set. 13. The method of claim 7 wherein the reconfigured logic array is configured with one or more technology types to execute the one or more processor states on the reconfigured logic array before executing the one or more processor states on the at least one processor and the at least one reconfigured logic array.

이 특허에 인용된 특허 (25)

Pannese, Patrick D., Applications of neural networks.
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Wirthlin Michael J. ; Hutchings Brad L., Dynamically-configurable digital processor using method for relocating logic array modules.
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Willis,John, Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization.
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Stamm, Reto; McGloin, Ciaran; McNicholl, David, Instruction processor and programmable logic device cooperative computing arrangement and method.
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Eskesen Frank Norman ; Hack Michel Henri Theodore ; Halim Nagui ; King Richard Pervin, Method and apparatus for protecting portions of memory by providing access requests to a communications area for process.
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Tseng, Ping-Sheng; Lin, Sharon Sheau-Pyng; Shen, Quincy Kun-Hsu; Tsai, Mike Mon Yen; Wang, Steven, Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic.
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Decker,Mark H., Method and system for specifying sets of instructions for selection by an instruction generator.
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Trimberger Stephen M., Method for compiling and executing programs for reprogrammable instruction set accelerator.
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Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
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Miranda, Tracy; Perry, Steven, Methods and apparatus for executing extended custom instructions.
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Pannese, Patrick D.; Kavathekar, Vinaya; van der Meulen, Peter, Methods and systems for controlling a semiconductor fabrication process.
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Wallach, Steven J.; Brewer, Tony, Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set.
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Estes Mark D., Polymorphic network methods and apparatus.
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Tanaka Youichi,JPX ; Nakai Futoshi,JPX ; Masuda Tatsuo,JPX, Programmable controller with a BPU that executes first-class instructions, a CPU that executes second-class instructions, and a skip instruction processing section that skips the current instruction .
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Rupp Charle R., Reconfigurable computer architecture for use in signal processing applications.
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Brookes, Peter; Hall, Andrew; Gray, Nigel, Simulation of hardware and software.
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Herron,Nigel G.; Ansari,Ahmad R.; Douglass,Stephen M.; Correale, Jr.,Anthony; DeBruyne,Leslie M., Speed verification of an embedded processor in a programmable logic device.
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Wicker, Jr., David J., State machine in a programmable logic device.
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Foster Mark J. ; Fakhruddin Saifuddin T. ; Walker James L. ; Mendelow Matthew B. ; Sun Jiming ; Brahman Rodman S. ; Krau Michael P. ; Willoughby Brian D. ; Maddix Michael D. ; Belt Steven L. ; Hovey , Suspend/resume capability for a protected mode microprocessor.
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Hammes,Jeffrey, System and method for converting control flow graph representations to control-dataflow graph representations.
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Poznanovic, Daniel; Hammes, Jeffrey; Krause, Lisa; Steidel, Jon, System and method for partitioning control-dataflow graph representations.
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Schiek,Richard, System for generating two-dimensional masks from a three-dimensional model using topological analysis.
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Mendel, David; Betz, Vaughn, Systems and methods for reducing static and total power consumption.
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James Roxby,Philip B.; Keller,Eric R., Using an embedded processor to implement a finite state machine.
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Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set 원문보기

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