초록 ▼

In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacr

In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.

대표청구항 ▼

1. A semiconductor device comprising: a semiconductor body comprising a first semiconductor material;a first gate electrode adjacent a second gate electrode, the first gate electrode and the second gate electrode disposed over an upper surface of the semiconductor body;a first sidewall spacer dispos

1. A semiconductor device comprising: a semiconductor body comprising a first semiconductor material;a first gate electrode adjacent a second gate electrode, the first gate electrode and the second gate electrode disposed over an upper surface of the semiconductor body;a first sidewall spacer disposed along a first sidewall of the first gate electrode;a second sidewall spacer disposed along a second sidewall of the second gate electrode, the first sidewall spacer and the second sidewall spacer facing each other;a shared source/drain region between the first sidewall spacer and the second sidewall spacer, wherein the shared source/drain region comprises the first semiconductor material on the upper surface of the semiconductor body;a first region within the shared source/drain region adjacent the first gate electrode comprising a second semiconductor material embedded therein;a second region within the shared source/drain region adjacent the second gate electrode comprising the second semiconductor material embedded therein; anda third region between the first and second regions, the third region separating the first region from the second region and comprising the first semiconductor material, wherein the first semiconductor material is different than the second semiconductor material. 2. The device of claim 1, wherein the first semiconductor material comprises silicon and the second semiconductor material comprises silicon germanium. 3. The device of claim 1, wherein the first semiconductor material comprises silicon and the second semiconductor material comprises silicon carbon. 4. The device of claim 1, wherein the first region has a first region length and the second region has a second region length, and wherein the first region length and the second region length are substantially the same length. 5. The device of claim 1, further comprising a trench isolation structure surrounding the first and second gate electrodes and the first and second regions. 6. A semiconductor device comprising: a semiconductor body comprising a first semiconductor material;a first gate electrode disposed over an upper surface of the semiconductor body;a first sidewall spacer disposed along a first sidewall of the first gate electrode;a second gate electrode disposed over the upper surface of the semiconductor body, the second gate electrode disposed adjacent to the first gate electrode;a second sidewall spacer disposed along a second sidewall of the second gate electrode; anda shared source/drain region between the first gate electrode and the second gate electrode, the shared source/drain region comprising the first semiconductor material on the upper surface of the semiconductor body, the shared source/drain region further comprising a first embedded region comprising a second semiconductor material and a second embedded region comprising a third semiconductor material, wherein the first embedded region is laterally separated from the second embedded region by the first semiconductor material, wherein the second semiconductor material and the third semiconductor material comprise the same material, and wherein the first semiconductor material comprises silicon and the second semiconductor material comprises silicon germanium. 7. The device of claim 6, wherein the semiconductor body comprises a semiconductor layer of a SOI substrate. 8. The device of claim 6, wherein the first embedded region is disposed within a first recess in the semiconductor body, and wherein the second embedded region is disposed within a second recess in the semiconductor body. 9. The device of claim 6, wherein the first embedded region is substantially aligned with the first sidewall spacer, and wherein the second embedded region is substantially aligned with the second sidewall spacer. 10. The device of claim 6, wherein the first gate electrode is insulated from the semiconductor body by a first gate dielectric and the second gate electrode is insulated from the semiconductor body by a second gate dielectric, and wherein the first and second gate dielectrics comprise silicon oxynitride (SiON), oxide-nitride-oxide (ONO), silicon nitride, HfO2, Hf silicate, Al2O3, ZrO2, Zr—Al—O, or Zr silicate. 11. The device of claim 6, wherein the first embedded region and the second embedded region extend above the upper surface of the semiconductor body. 12. A semiconductor device comprising: a semiconductor body comprising a semiconductor material;a first gate electrode disposed in a first region of the semiconductor body, the first gate electrode comprising a first sidewall spacer;a second gate electrode disposed in a second region of the semiconductor body, the second gate electrode comprising a second sidewall spacer, wherein the first sidewall spacer is opposite the second sidewall spacer; anda shared source/drain region disposed between the first gate electrode and the second gate electrode, wherein the shared source/drain region comprises a third region comprising the semiconductor material, a fourth region and a fifth region, wherein the fourth region and the fifth region comprise a compound semiconductor material, wherein the third region is laterally adjacent to the fourth region and laterally adjacent to the fifth region, and wherein the semiconductor material and the compound semiconductor material are different. 13. The device of claim 12, wherein the fourth region is substantially aligned with the first sidewall spacer, and wherein the fifth region is substantially aligned with the second sidewall spacer. 14. The device of claim 13, wherein the fourth region comprises a first length and the fifth region comprises a second length, and wherein the first length is the same as the second length. 15. The device of claim 14, wherein the compound semiconductor material comprises silicon germanium. 16. The device of claim 14, wherein the compound semiconductor material comprises silicon carbon. 17. The device of claim 14, wherein the first gate electrode is insulated from the semiconductor body by a first gate dielectric and the second gate electrode is insulated from the semiconductor body by a second gate dielectric, and wherein the first and second gate dielectrics comprise silicon oxynitride (SiON), oxide-nitride-oxide (ONO), silicon nitride, HfO2, Hf silicate, Al2O3, ZrO2, Zr—Al—O, or Zr silicate. 18. The device of claim 12, wherein the third region, the fourth region and the fifth region are located at a top surface of the semiconductor body. 19. A semiconductor device comprising: a semiconductor body comprising a first semiconductor material;a first gate electrode disposed over an upper surface of the semiconductor body;a first sidewall spacer disposed along a first sidewall of the first gate electrode;a second gate electrode disposed over the upper surface of the semiconductor body, the second gate electrode disposed adjacent to the first gate electrode;a second sidewall spacer disposed along a second sidewall of the second gate electrode; anda shared source/drain region between the first gate electrode and the second gate electrode, the shared source/drain region comprising the first semiconductor material on the upper surface of the semiconductor body, the shared source/drain region further comprising a first embedded region comprising a second semiconductor material and a second embedded region comprising a third semiconductor material, wherein the first embedded region is laterally separated from the second embedded region by the first semiconductor material, wherein the second semiconductor material and the third semiconductor material comprise the same material, and wherein the first semiconductor material comprises silicon and the second semiconductor material comprises silicon carbon.