IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0556870
(2009-09-10)
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등록번호 |
US-8629509
(2014-01-14)
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발명자
/ 주소 |
- Ryu, Sei-Hyung
- Zhang, Qingchun
|
출원인 / 주소 |
|
대리인 / 주소 |
Myers Bigel Sibley & Sajovec
|
인용정보 |
피인용 횟수 :
3 인용 특허 :
160 |
초록
▼
High power insulated gate bipolar junction transistors are provided that include a wide band gap semiconductor bipolar junction transistor (“BJT”) and a wide band gap semiconductor MOSFET that is configured to provide a current to the base of the BJT. These devices further include a minority carrier
High power insulated gate bipolar junction transistors are provided that include a wide band gap semiconductor bipolar junction transistor (“BJT”) and a wide band gap semiconductor MOSFET that is configured to provide a current to the base of the BJT. These devices further include a minority carrier diversion semiconductor layer on the base of the BJT and coupled to the emitter of the BJT, the minority carrier diversion semiconductor layer having a conductivity type opposite the conductivity type of the base of the BJT and forming a heterojunction with the base of the BJT.
대표청구항
▼
1. A high power insulated gate bipolar junction transistor (“IGBT”), comprising: a wide band gap semiconductor bipolar junction transistor (“BJT”) having a collector, an emitter and a base;a MOSFET having a gate, a source region, a drain region and a channel region extending between the source regio
1. A high power insulated gate bipolar junction transistor (“IGBT”), comprising: a wide band gap semiconductor bipolar junction transistor (“BJT”) having a collector, an emitter and a base;a MOSFET having a gate, a source region, a drain region and a channel region extending between the source region and the drain region, wherein the source region, the drain region and the channel region comprise a first wide band gap semiconductor material, and wherein the MOSFET is configured to provide a current to the base of the BJT; anda minority carrier diversion semiconductor layer between the base of the BJT and the gate of the MOSFET configured to divert a portion of the minority carrier current flow through the IGBT, the minority carrier diversion semiconductor layer having a conductivity type opposite the conductivity type of the base of the BJT and forming a heterojunction with the base of the BJT. 2. The high power IGBT of claim 1, wherein the wide band gap semiconductor BJT comprises a BJT having a silicon carbide base, a silicon carbide collector and a silicon carbide emitter, and wherein the MOSFET comprises a silicon carbide MOSFET. 3. The high power IGBT of claim 2, wherein the minority carrier diversion semiconductor layer comprises a doped polysilicon layer. 4. The high power IGBT of claim 3, wherein the IGBT includes: an n-type injection layer;a p-type layer on the n-type injection layer;an n-well in an upper portion of the p-type layer;a heavily-doped p-type layer in an upper region of the n-well; anda gate dielectric layer between the gate and the n-well. 5. The high power IGBT of claim 4, wherein the p-type layer on the n-type injection layer comprises a p-type base layer that has a doping concentration that is less than a doping concentration of the heavily-doped p-type layer, and a p-type drift layer on the p-type base layer having a doping concentration that is less than the doping concentration of the p-type base layer. 6. The high power IGBT of claim 5, wherein the doped polysilicon layer is between the gate dielectric layer and the p-type drift layer. 7. The high power IGBT of claim 6, wherein a first channel region of the n-well that is on a first side of the heavily-doped p-type layer and that is under the gate electrode is doped at a concentration that is substantially the same as a second region of the n-well that is on the opposite side of the heavily-doped p-type layer. 8. The high power IGBT of claim 6, wherein a top surface of the doped polysilicon layer is even with or below a top surface of the n-well. 9. The high power IGBT of claim 4, wherein a thickness of a middle portion of the gate dielectric layer that is on the doped polysilicon layer is greater than a thickness of an end portion of the gate insulation layer that is on the n-well. 10. The high power IGBT of claim 4, further comprising an electrical connection between the heavily-doped p-type layer and the minority carrier diversion semiconductor layer. 11. The high power IGBT of claim 2, wherein the minority carrier diversion semiconductor layer is not a wide band gap semiconductor layer. 12. The high power IGBT of claim 1, wherein the a channel of the MOSFET comprises a silicon carbide channel. 13. The high power IGBT of claim 1, wherein the collector of the BJT has a first conductivity type and is disposed in a well region that has a second conductivity type, wherein the minority carrier diversion semiconductor layer has a second conductivity type, and wherein a semiconductor region having the first conductivity type is disposed between the well region and the minority carrier diversion semiconductor layer. 14. A high power insulated gate bipolar junction transistor (“IGBT”), comprising: a wide band gap semiconductor bipolar junction transistor (“BJT”) having a collector, an emitter and a base;a MOSFET that is configured to provide a current to the base of the BJT; anda minority carrier diversion semiconductor layer between the base of the BJT and a gate of the MOSFET that is configured to divert a portion of the minority carrier current flow through the IGBT, the minority carrier diversion semiconductor layer having a conductivity type opposite the conductivity type of the base of the BJT and forming a heterojunction with the base of the BJT,wherein the wide band gap semiconductor BJT comprises a silicon carbide BJT,wherein the MOSFET comprises a silicon carbide MOSFET,wherein the minority carrier diversion semiconductor layer comprises a doped polysilicon layer,wherein the IGBT includes an n-type injection layer, a p-type layer on the n-type injection layer, an n-well in an upper portion of the p-type layer, a heavily-doped p-type layer in an upper region of the n-well, a gate dielectric layer on the n-well and the heavily-doped p-type layer, and a gate electrode on the gate dielectric layer,wherein the p-type layer on the n-type injection layer comprises a p-type base layer that has a doping concentration that is less than a doping concentration of the heavily-doped p-type layer, and a p-type drift layer on the p-type base layer having a doping concentration that is less than the doping concentration of the p-type base layer,wherein the doped polysilicon layer is between the gate dielectric layer and the p-type drift layer, andwherein a top surface of the doped polysilicon layer is farther above the n-type injection layer than is a top surface of the n-well. 15. A high power p-channel silicon carbide insulated gate bipolar junction transistor (“IGBT”), comprising: an n-type silicon carbide injection layer;a p-type silicon carbide base layer on the n-type silicon carbide injection layer;a p-type silicon carbide drift layer on the p-type silicon carbide base layer opposite the n-type silicon carbide injection layer;a silicon carbide n-well in an upper portion of the p-type silicon carbide drift layer;a p-type silicon carbide emitter region in the silicon carbide n-well and directly contacting the silicon carbide n-well;an n-type silicon layer on the p-type silicon carbide drift layer opposite the p-type silicon carbide base layer;a gate insulation layer on the silicon carbide n-well and the n-type silicon layer; anda gate electrode on the gate insulation layer opposite the silicon carbide n-well and the n-type silicon layer. 16. A high power p-channel silicon carbide insulated gate bipolar junction transistor (“IGBT”), comprising; an n-type silicon carbide injection layer;a p-type silicon carbide base layer on the n-type silicon carbide injection layer;a p-type silicon carbide drift layer on the p-type silicon carbide base layer opposite the n-type silicon carbide injection layer;a silicon carbide n-well in an upper portion of the p-type silicon carbide drift layer;an n-type silicon layer on the p-type silicon carbide drift layer opposite the p-type silicon carbide base layer;a gate insulation layer on the silicon carbide n-well and the n-type silicon layer;a gate electrode on the gate insulation layer opposite the silicon carbide n-well and the n-type silicon layer; anda p-type silicon carbide emitter layer in an upper surface of the silicon carbide n-well,wherein the n-type silicon layer is electrically connected to the p-type silicon carbide emitter layer. 17. The high power p-channel silicon carbide IGBT of claim 16, wherein the silicon layer comprises a minority carrier diverter that forms a heterojunction with the p-type silicon carbide drift layer. 18. The high power p-channel silicon carbide IGBT of claim 17, further comprising an n-type silicon carbide substrate on the n-type silicon carbide injection layer opposite the p-type silicon carbide base layer, wherein a top surface of the silicon layer is farther above the n-type silicon carbide substrate than is a top surface of the silicon carbide n-well. 19. The high power p-channel silicon carbide IGBT of claim 17, wherein a top surface of the silicon layer is even with or below a top surface of the silicon carbide n-well. 20. A high power insulated gate bipolar junction transistor (“IGBT”) that includes a silicon carbide bipolar junction transistor (“BJT”) and a MOSFET, the IGBT comprising: a plurality of silicon carbide layers that include first and second silicon carbide well regions; anda doped semiconductor layer that forms a p-n heterojunction with a first of the plurality of silicon carbide layers, the doped semiconductor layer disposed between the first and second silicon carbide well regions;wherein the silicon carbide BJT is located within the plurality of silicon carbide layers;wherein a source region and a drain region of the MOSFET are located within the plurality of silicon carbide layers, and a gate electrode of the MOSFET is on the doped semiconductor layer; andwherein the doped semiconductor layer is configured to provide a minority carrier current path between the first and second well regions. 21. The high power IGBT of claim 20, wherein the doped semiconductor layer comprises a doped silicon layer. 22. The high power IGBT of claim 21, wherein the doped silicon layer comprises a doped polysilicon minority carrier diverter. 23. The high power IGBT of claim 22, wherein a top surface of the doped polysilicon layer is farther above an n-type substrate of the IGBT than is a top surface of a collector region of the BJT. 24. The high power IGBT of claim 22, wherein a top surface of the doped polysilicon layer is even with or below a top surface of the collector region of the BJT. 25. The high power IGBT of claim 20, wherein the doped semiconductor layer is between a base of the BJT and the gate electrode of the MOSFET.
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