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Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/29
출원번호 US-0235442 (2005-09-26)
등록번호 US-8629566 (2014-01-14)
발명자 / 주소
  • Shivkumar, Bharat
  • Cheah, Chuan
출원인 / 주소
  • International Rectifier Corporation
대리인 / 주소
    Farjami & Farjami LLP
인용정보 피인용 횟수 : 1  인용 특허 : 42

초록

A multichip module has a substrate, which receives several flip chip and for other semiconductor die on one surface and has vias extending through the substrate from the flip chip bottom electrodes to solder ball electrodes on the bottom of the substrate. Passive components are also mounted on the t

대표청구항

1. An MCM device comprising a flat thin insulation substrate having parallel top and bottom surfaces; a plurality of laterally displaced conductive vias extending between said top and bottom surfaces;a flip chip semiconductor die having top and bottom surfaces and having at least first and second el

이 특허에 인용된 특허 (42)

  1. Juskey Frank J. (Coral Springs FL) Hendricks Douglas W. (Boca Raton FL), Anchoring method for flow formed integrated circuit covers.
  2. Toy Hilton T. ; Sherif Raed A., Apparatus for controlling thermal interface gap distance.
  3. Covell ; II James H. ; Bolde Lannie R. ; Edwards David L. ; Goldmann Lewis S. ; Gruber Peter A. ; Toy Hilton T., Cast metal seal for semiconductor substrates and process thereof.
  4. Liang Louis H. (Los Altos CA), Design and sealing method for semiconductor packages.
  5. Sheng Tsung Liu TW, Electronic package with surface-mountable device built therein.
  6. Jimarez Miguel A. ; Perrino Marybeth ; Tran Son K. ; Wu Tien Y.,SGX, Encapsulated chip module and method of making same.
  7. Tsao Pei-Haw,TWX, Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength.
  8. Selna Erich (Mountian View CA) Ettehadieh Ehsan (Albany CA) LaGassa James (Cupertino CA), Heat sink and cover for tab integrated circuits.
  9. Huang Chien-Ping,TWX ; Jao Jui-Meng,TWX, Heat-dissipating device for integrated circuit package.
  10. Hundt Michael J. (Lewisville TX), IC package having direct attach backup battery.
  11. Lee,Young Min; Kwak,Kyu Sub, Land grid array module.
  12. Yukio Yamaguchi JP, Lead frame, resin-molded semiconductor device, and method for manufacturing the same.
  13. Lee Hee Gook,KRX, Lead on chip package.
  14. Hong, Harry Kam Cheng; Lek, Hu Ah; Nadarajah, Santhiran; Wan, Sharon Ko Mei; Yeen, Chan Peng; Bayan, Jaime; Spalding, Peter Howard, Locking of mold compound to conductive substrate panels.
  15. Rauchmaul Siegfried (Munich DEX) Schmidt Hans-Fr. (Eurasburg DEX) Bednarz Juergen (Penzberg DEX) Horsmann Karl-Heinz (Munich DEX) Criens Ralf (Munich DEX) Scheffler Horst (Munich DEX) Peltz Hanns-Hei, Method and an encapsulation for encapsulating electrical or electronic components or assemblies.
  16. Brand,Joseph M., Method and apparatus for removing encapsulating material from a packaged microelectronic device.
  17. Chen Tsung-Chieh,TWX ; Chen Chun-Liang,TWX ; Liao Kuang-Ho,TWX, Method for wire bonding a chip to a substrate with recessed bond pads and devices formed.
  18. Sheppard Robert P. ; Combs Edward G., Method of manufacturing a flexible integrated circuit package utilizing an integrated carrier ring/stiffener.
  19. Tsunoda Shigeharu,JPX ; Saeki Junichi,JPX ; Yoshida Isamu,JPX ; Ooji Kazuya,JPX ; Honda Michiharu,JPX ; Kitano Makoto,JPX ; Yoneda Nae,JPX ; Eguchi Shuji,JPX ; Nishi Kunihiko,JPX ; Anjoh Ichiro,JPX ;, Method of manufacturing a semiconductor device having a ball grid array package structure using a supporting frame.
  20. Chia Chok J. ; Lim Seng-Sooi ; Low Qwai H., Molded array integrated circuit package.
  21. Glenn Thomas P., Mounting having an aperture cover with adhesive locking feature for flip chip optical integrated circuit device.
  22. Hosoya Futoshi,JPX, Multi-chip packaging structure having chips sealably mounted on opposing surfaces of substrates.
  23. Golubic Theodore R. (Phoenix AZ) Polka Frank E. (Phoenix AZ) Webb Brian A. (Mesa AZ), Multi-level semiconductor package.
  24. Variot Patrick (San Jose CA) Chia Chok J. (Campbell CA), Overmolded semiconductor package.
  25. Hamzehdoost Ahmad (Sacramento CA) Huang Chin-Ching (San Jose CA), Package structure and method for reducing bond wire inductance.
  26. Marrs Robert C. (Scottsdale AZ), Packaged semiconductor die including heat sink with locking feature.
  27. Bolken,Todd O.; Baerlocher,Cary J.; Corisis,David J.; Cobbley,Chad A., Packages for semiconductor die.
  28. Hodges Joe W., Packaging for bare dice employing EMR-sensitive adhesives.
  29. Hegel Uli (Novato CA), Plastic pin grid array package with locking pillars.
  30. Ting Chiu H. (Saratoga CA), Process for fabricating sealed semiconductor chip using silicon nitride passivation film.
  31. Nagaraj Benamanahalli K. (Phoenix AZ) Olson Timothy L. (Phoenix AZ) Chaudhry Udey (Mesa AZ), Reduced stress plastic package.
  32. Ishida Yoshihiro (Tokorozawa JPX) Komatsu Katsuji (Kawagoe JPX) Mimura Seiichi (Kawagoe JPX) Takenouchi Kikuo (Higashimurayama JPX) Yabe Isao (Tokorozawa JPX) Ichikawa Shingo (Sayama JPX) Shimada Yos, Resin encapsulated semiconductor device.
  33. Lloyd R. Rodenbeck ; Donald R. Potter, Semiconductor and flip chip packages and method having a back-side connection.
  34. Tomita Yoshihiro,JPX, Semiconductor device.
  35. Takahashi Takuya,JPX ; Katsumata Akio,JPX, Semiconductor device and method for manufacturing the same.
  36. Jiang Tongbi ; Cobbley Chad A., Semiconductor die back side surface and method of fabrication.
  37. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
  38. Parthasarathi Arvind ; Mahulikar Deepak, Semiconductor package with molded plastic body.
  39. Vaiyapuri, Venkateshwaran, Semiconductor/printed circuit board assembly, and computer system.
  40. Juskey Frank J. (Coral Springs FL) Suppelsa Anthony B. (Coral Springs FL), Thermally conductive integrated circuit package with radio frequency shielding.
  41. Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
  42. James M. Wark ; Salman Akram, Thin film capacitor coupons for memory modules and multi-chip modules.

이 특허를 인용한 특허 (1)

  1. Ashrafzadeh, Ahmad R.; Mikolajczak, Adrian; Wu, Chung-Lin; Estacio, Maria Cristina, Packaged semiconductor devices and methods of manufacturing.
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