IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0119823
(2008-09-19)
|
등록번호 |
US-8629716
(2014-01-14)
|
국제출원번호 |
PCT/SG2008/000360
(2008-09-19)
|
§371/§102 date |
20110609
(20110609)
|
국제공개번호 |
WO2010/033080
(2010-03-25)
|
발명자
/ 주소 |
|
출원인 / 주소 |
- Agency for Science, Technology and Research
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
16 |
초록
▼
A modulator, a demodulator and a modulator-demodulator are provided. A modulator includes a first intermediate signal processing path adapted to route a first intermediate signal; a second intermediate signal processing path adapted to route a second intermediate signal; a first amplifier coupled in
A modulator, a demodulator and a modulator-demodulator are provided. A modulator includes a first intermediate signal processing path adapted to route a first intermediate signal; a second intermediate signal processing path adapted to route a second intermediate signal; a first amplifier coupled into the first intermediate signal processing path; a second amplifier coupled into the second intermediate signal processing path; and a chopper circuit coupled into the first intermediate signal processing path; wherein the chopper circuit is adapted to process the first intermediate signal in dependence on first baseband data; wherein the first amplifier is adapted to amplify the first intermediate signal processed by the chopper circuit in dependence on second baseband data; and wherein the second amplifier is adapted to amplify the second intermediate signal in dependence on the second baseband data.
대표청구항
▼
1. A demodulator comprising: an amplitude demodulating path adapted to route a carrier signal;a frequency demodulating path adapted to route the same carrier signal;a mode control unit coupled to an output terminal of the amplitude demodulating path and an output terminal of the frequency demodulati
1. A demodulator comprising: an amplitude demodulating path adapted to route a carrier signal;a frequency demodulating path adapted to route the same carrier signal;a mode control unit coupled to an output terminal of the amplitude demodulating path and an output terminal of the frequency demodulating path; anda pulse-width modulator coupled into the frequency demodulating path;wherein the mode control unit is adapted to control different modes of demodulation;wherein, when the demodulator is operated in a controllable weight amplitude frequency shift keying (CW-AFSK) mode, the mode control unit is adapted to control the pulse-width of the pulse-width modulator in dependence on an output signal of the amplitude demodulating path;wherein the modes of demodulation further comprise one or more of a group consisting of amplitude shift keying (ASK) mode, frequency shift keying (FSK) mode and dual channel amplitude frequency shift keying (DC-AFSK) mode. 2. The demodulator of claim 1, wherein the amplitude demodulating path comprises an amplitude shift keying demodulating unit, an output terminal of the amplitude shift keying demodulating unit being coupled to an input terminal of the mode control unit. 3. The demodulator of claim 2, wherein the frequency demodulating path comprises a frequency shift keying demodulating unit, the frequency shift keying demodulating unit comprising the pulse-width modulator. 4. The demodulator of claim 3, further comprising a slicer coupled to an output terminal of the mode control unit. 5. The demodulator of claim 4, wherein the slicer has an efficient DC offset canceller, a peak detector and a valley detector;wherein the efficient DC offset canceller is implemented based on DC offset cancellation loop (DC offset feedback loop) or implemented based on dynamically setting a threshold of the slicer to a mean value of an input signal of the slicer;wherein the input signal of the slicer is supplied to the peak detector and the valley detector; andwherein the mean value of the input signal of the slicer is an average signal of an output of the peak detector and an output of the valley detector. 6. The demodulator of claim 4, wherein, when the demodulator is operated in the controllable weight amplitude frequency shift keying (CW-AFSK) mode, the mode control unit is adapted to couple an output terminal of the frequency shift keying demodulating unit to an input terminal of the slicer. 7. The demodulator of claim 3, wherein the frequency shift keying demodulating unit further comprises a zero-crossing detector, an output terminal of the zero-crossing detector being coupled to an input terminal of the pulse-width modulator. 8. The demodulator of claim 7, wherein the zero-crossing detector of the frequency shift keying demodulator is operable in a first accuracy mode and a second accuracy mode. 9. The demodulator of claim 8, wherein in the first accuracy mode, the zero-crossing detector uses: a filter bank;a first comparator having a first input terminal of the first comparator coupled to a first output terminal of the filter bank, a second input terminal of the first comparator coupled to a second output terminal of the filter bank, and an output terminal;a second comparator having a first input terminal of the second comparator coupled to a third output terminal of the filter bank, a second input terminal of the second comparator coupled to a fourth output terminal of the filter bank, and an output terminal; anda XOR gate having a first input terminal coupled to the output terminal of the first comparator and a second input terminal coupled to the output terminal of the second comparator. 10. The demodulator of claim 8, wherein in the second accuracy mode, the zero-crossing detector uses an instant phase calculator and an analog to pulse train converter, an output terminal of the instant phase calculator being coupled to an input terminal of the analog to pulse train converter. 11. The demodulator of claim 10, wherein the instant phase calculator comprises: a filter bank;a first transconductor having a first input terminal coupled to a first output terminal of the filter bank, a second input terminal coupled to a second output terminal of the filter bank, and an output terminal;a rectifier having a first input terminal coupled to a third output terminal of the filter bank, a second input terminal coupled to a fourth output terminal of the filter bank, and an output terminal;a peak detector having a first input terminal coupled to the third output terminal of the filter bank, a second input terminal coupled to the fourth output terminal of the filter bank, and an output terminal;a valley detector having a first input terminal coupled to the third output terminal of the filter bank, a second input terminal coupled to the fourth output terminal of the filter bank, and an output terminal;a second transconductor having a first input terminal coupled to the output terminal of the peak detector, a second input terminal coupled to the output terminal of the valley detector, and an output terminal;a summing device having a first input terminal coupled to the output terminal of the rectifier, a second input terminal coupled to the output terminal of the second transconductor, and an output terminal;a scaling device having a first input terminal coupled to the output terminal of the summing device, a second input terminal coupled to the output terminal of the first transconductor, and an output terminal; anda transimpedance amplifier having an input terminal coupled to the output terminal of the scaling device, and an output terminal coupled to the input terminal of the analog to pulse train converter. 12. The demodulator of claim 11, wherein the summing device is adapted to combine an output signal of the rectifier and an output signal of the second transconductor;wherein the scaling device is adapted to divide an output signal of the first transconductor by an output signal of the summing device. 13. The demodulator of claim 11, wherein the analog to pulse train converter comprises: a plurality of resistors connected in series, wherein the number of resistors is odd;a plurality of comparators, each comparator having a first input terminal coupled to the output terminal of the transimpedance amplifier and a second input terminal coupled to an individual connection connecting two adjacent resistors of the plurality of resistors, and an output terminal;a plurality of XOR gates, each XOR gate having two input terminals and one output terminal, wherein the two input terminals of each XOR gate are coupled to outputs of two adjacent comparators;an OR gate, each input terminal of which being coupled to the output terminal of one of the plurality of XOR gates. 14. The demodulator of claim 13, wherein, when a further resistor is connected to the plurality of resistors in series, the analog to pulse train converter further comprises a further comparator having a first input terminal coupled to the output terminal of the transimpedance amplifier, and a second input terminal coupled to a further connection connecting the further resistor and an adjacent resistor, and an output terminal coupled to the input terminal of the OR gate. 15. The demodulator of claim 3, wherein the frequency shift keying demodulating unit further comprises a filter, an input terminal of the filter being coupled to the output terminal of the pulse-width modulator. 16. The demodulator of claim 1, wherein, when the demodulator is operated in the controllable weight amplitude frequency shift keying (CW-AFSK) mode, the mode control unit is adapted to provide a scaling device to receive the output signal of the amplitude demodulating path, to scale the output signal of the amplitude demodulating path and to supply the scaled output signal of the amplitude demodulating path to the pulse-width modulator, the pulse-width of the pulse-width modulator being controlled by the scaled output signal of the amplitude demodulating path. 17. The demodulator of claim 16, wherein the scaling device is adapted to scale the output signal of the amplitude demodulating path by multiplying the output signal of the amplitude demodulating path with a control signal received by the scaling device. 18. The demodulator of claim 1, wherein, when the demodulator is operated in the amplitude shift keying (ASK) mode, the mode control unit is adapted to couple the output terminal of the amplitude shift keying demodulating unit to the input terminal of the slicer and to deactivate the frequency shift keying demodulating unit. 19. The demodulator of claim 18, wherein the amplitude shift keying demodulating unit comprises a rectifier and a filter, an input terminal of the filter being coupled to an output terminal of the rectifier. 20. The demodulator of claim 19, wherein the rectifier of the amplitude shift keying demodulator comprises: a first half wave transconductance rectifier having a first input terminal, a second input terminal, and an output terminal; anda second half wave transconductance rectifier having a first input terminal, a second input terminal, and an output terminal;wherein the first input terminal of the first half wave transconductance rectifier is coupled to the second input terminal of the second half wave transconductance rectifier;wherein the second input terminal of the first half wave transconductance rectifier is coupled to the first input terminal of the second half wave transconductance rectifier; andwherein the output terminal of the first half wave transconductance rectifier is coupled to the output terminal of the second half wave transconductance rectifier. 21. The demodulator of claim 20, wherein the rectifier of the amplitude shift keying demodulator further comprises a load resistor and a load current source;wherein a first end of the load resistor is coupled to a supply voltage of the rectifier;wherein the output terminal of the first half wave transconductance rectifier and the output terminal of the second half wave transconductance rectifier are coupled to a second end of the load resistor and an input terminal of the load current source;wherein an output terminal of the load current source is coupled to ground;wherein the output terminal of the first half wave transconductance rectifier and the output terminal of the second half wave transconductance rectifier are coupled to the input terminal of the filter of the amplitude shift keying demodulating unit. 22. The demodulator of claim 1, wherein, when the demodulator is operated in the frequency shift keying (FSK) mode, the mode control unit is adapted to couple an output terminal of the frequency shift keying demodulating unit to the input terminal of the slicer, to deactivate the amplitude shift keying demodulating unit, and to set a pulse-width control signal supplied to the pulse-width modulator to a suitable constant value. 23. The demodulator of claim 1, wherein, when the demodulator is operated in the dual channel amplitude frequency shift keying (DC-AFSK) mode, the mode control unit is adapted to couple the output terminal of the amplitude shift keying demodulating unit and the output terminal of the frequency shift keying demodulating unit to the input terminal of the slicer, and to set the pulse-width control signal supplied to the pulse-width modulator to a suitable constant value.
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