초록 ▼

Active inrush current control includes activating a load, the activating causing inrush current to flow, switching a semiconductor switching device to a current limiting state in response to the inrush current flow, the current limiting state being one of at least three states of the semiconductor s

Active inrush current control includes activating a load, the activating causing inrush current to flow, switching a semiconductor switching device to a current limiting state in response to the inrush current flow, the current limiting state being one of at least three states of the semiconductor switching device and the current limiting state dissipating the inrush current, and switching the semiconductor device to a full current flow state in response to the dissipating, the full current flow state not inhibiting current flow.

대표청구항 ▼

1. A method of active inrush current control, comprising: activating a load, the activating causing inrush current to flow;switching a semiconductor switching device to a current limiting state in response to the inrush current flow, the current limiting state being one of at least three states of t

1. A method of active inrush current control, comprising: activating a load, the activating causing inrush current to flow;switching a semiconductor switching device to a current limiting state in response to the inrush current flow, the current limiting state being one of at least three states of the semiconductor switching device and the current limiting state dissipating the inrush current; andswitching the semiconductor switching device to a full current flow state in response to the dissipating, the full current flow state not inhibiting current flow,wherein the semiconductor switching device includes two transistors disposed and configured to control current flow in the at least three states, andwherein the transistors operate within a same state of the at least three states. 2. The method of claim 1, wherein: a first state of the at least three states blocks current flow;a second state of the at least three states is the current limiting state; anda third state of the at least three states is the full current flow state. 3. The method of claim 2, wherein the current limiting state is a variable state variably limiting current flow. 4. The method of claim 2, wherein the current limiting state is a linear operating state of at least one transistor of the semiconductor switching device. 5. The method of claim 1, further comprising switching the semiconductor switching device to a current blocking state, the current blocking state deactivating the load. 6. The method of claim 1, applying a bias voltage to a transistor of the semiconductor switching device to switch states of the semiconductor switching device. 7. The method of claim 6, wherein the bias voltage is one of at least three voltage levels. 8. The method of claim 1, further comprising a DC link capacitor and a transformer in communication with the load, the DC link capacitor and the transformer providing the inrush current. 9. A semiconductor switching device for active inrush current control, comprising: a first transistor disposed and configured to control current flow in at least three states;a first voltage suppression device in communication with the first transistor;a second transistor disposed and configured to control current flow in at least three states, an emitter of the second transistor in communication with an emitter of the first transistor;a second voltage suppression device in communication with the second transistor; anda signaling source in communication with the first transistor and the second transistor, the signaling source disposed and configured to provide different bias voltages to the transistors, the different biasing voltages changing the states of the transistors to a different states of at least three operating states in unison. 10. The semiconductor switching device of claim 9, wherein the first and second voltage suppression devices are transient voltage suppression diodes or zener diodes. 11. The semiconductor switching device of claim 9, wherein the first and second transistors are insulated-gate bipolar transistors or field-effect transistors. 12. The semiconductor switching device of claim 9, further comprising: a first bypass and protection diode coupled across the emitter and a collector of the first transistor; anda second bypass and protection diode coupled across the emitter and a collector of the second transistor; wherein the first and second bypass and protection diodes alternate between forward and reverse bias in response to a direction of inrush current flow. 13. The semiconductor switching device of claim 9, wherein: a first state of the at least three states blocks current flow;a second state of the at least three states limits current flow; anda third state of the at least three states does not inhibit current flow.