IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0604812
(2009-10-23)
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등록번호 |
US-8638076
(2014-01-28)
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발명자
/ 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
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인용정보 |
피인용 횟수 :
2 인용 특허 :
61 |
초록
▼
Hysteretic performance with fixed frequency may be achieved in controlling a power/voltage regulator, by adapting fixed frequency PWM (Pulse Width Modulation) to current-mode hysteretic control. In steady state, the current waveform may be inferred without having to measure the current. In current-m
Hysteretic performance with fixed frequency may be achieved in controlling a power/voltage regulator, by adapting fixed frequency PWM (Pulse Width Modulation) to current-mode hysteretic control. In steady state, the current waveform may be inferred without having to measure the current. In current-mode control, the current may be adjusted proportional to the error voltage. The change in load current may be related to the change in duty-cycle, and the change in duty-cycle may be related to the error voltage, with the change in duty-cycle expressed as a function of the error voltage, to establish current-mode control. This current-mode control may be adapted to perform current-mode hysteretic, if instead of duty-cycle, the same duty-cycle or current shift was effected by a change in phase. A fraction of ripple current (Forc) may be defined as a specified fraction of the peak-to-peak ripple current, establishing a linear relationship between the Forc and the ripple current.
대표청구항
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1. A system for controlling an output of a power regulator, the system comprising: a main control loop configured to generate an error signal based on: an output of the power regulator; anda reference signal;wherein the main control loop is further configured to generate a first control signal based
1. A system for controlling an output of a power regulator, the system comprising: a main control loop configured to generate an error signal based on: an output of the power regulator; anda reference signal;wherein the main control loop is further configured to generate a first control signal based on the error signal to control steady state behavior of the output of the power regulator; anda secondary control loop comprised within the main control loop, and configured to: generate a second control signal based on the error signal; andcontrol transient response of the output of the power regulator using at least the second control signal. 2. The system of claim 1, wherein in generating the second control signal, the secondary control loop is configured to emulate a current-mode hysteretic control of the output of the power regulator according to the steady state behavior. 3. The system of claim 1, wherein the first control signal is configured to control generation of a digital pulse-width modulated (PWM) signal configured to power an output stage of the power regulator, wherein the output stage of the power regulator is configured to provide the output of the power regulator. 4. The system of claim 3, wherein the first control signal is configured to control a duty-cycle of the PWM signal. 5. The system of claim 3, wherein the second control signal is configured to shift the PWM signal. 6. The system of claim 5, wherein the output of the power regulator is configured to couple to an inductor; wherein the second control signal is configured to shift the PWM signal by an amount corresponding to a fraction of a ripple current generated in the inductor. 7. A method for controlling an output of a power regulator, the method comprising: generating an error signal based on the output of the power regulator and a reference voltage;generating a first control signal based on the error signal;controlling steady state behavior of the output of the power regulator using the first control signal;generating a second control signal based on the error signal; andcontrolling transient response of the output of the power regulator using the second control signal. 8. The method of claim 7; wherein said controlling the steady state behavior of the output of the power regulator comprises adjusting a first power signal configured to control an output stage of the power regulator; andwherein said controlling the transient response of the output of the power regulator comprises adjusting a phase of the first power signal. 9. The method of claim 8, wherein said adjusting the phase of the first power signal is performed instantaneously. 10. The method of claim 8, wherein the first power signal is a pulse-width modulated (PWM) signal; wherein said adjusting the first power signal comprises adjusting a duty-cycle of the PWM signal; andwherein said adjusting the phase of the first power signal comprises shifting the PWM signal. 11. The method of claim 8, wherein said adjusting the phase of the first power signal comprises: calculating a target count value based on a required phase shift for the first power signal and a net phase shift of the first power signal;counting cycle segments of a frequency of the first power signal; andtoggling the first power signal when a current count value of said counting is greater than or equal to the target count value. 12. The method of claim 11, further comprising: subsequent to each instance of said toggling the first power signal, performing: recalculating the net phase shift based on the required phase shift, the current count value and the target count value;restarting said counting from an initial value; andtoggling the first power signal when the current count value of said counting is greater than or equal to the target count value. 13. A method for performing hysteretic control on an output of a voltage regulator, the method comprising: inferring a current waveform corresponding to an unmeasured current developed in response to an output voltage provided at the output of the voltage regulator wherein said inferring is performed based at least on an established steady state behavior of the output of the voltage regulator;obtaining an error voltage based on the output voltage of the voltage regulator and a reference voltage; andadjusting an inductor current proportional to the error voltage, according to the inferred current waveform, wherein the inductor current is developed at least in response to the output voltage. 14. The method of claim 13, wherein said adjusting the inductor current comprises controlling the output voltage. 15. The method of claim 14, wherein said controlling the output voltage comprises: generating a first control signal from the error voltage, the first control signal having a fixed frequency; andcontrolling the output voltage using the first control signal. 16. The method of claim 14, wherein said adjusting the inductor current further comprises shifting the first control signal according to the inferred current waveform. 17. The method of claim 16, wherein said shifting the first control signal comprises: generating a second control signal from the error voltage, according to the inferred current waveform; andshifting the first control signal using the second control signal. 18. The method of claim 16, wherein said shifting the first control signal comprises shifting the first control signal by a specified amount that corresponds to a value of the error voltage and is determined from a slope of the inferred current waveform. 19. A voltage regulator comprising: a power stage configured to provide a regulated output voltage; anda control stage configured to: generate a pulse-width-modulated (PWM) signal that controls the power stage and therefore a value of the regulated output voltage;determine a duty-cycle value of the PWM signal based on a reference voltage and the regulated output voltage; andphase shift the PWM signal according to an inferred slope of an unmeasured current developed responsive to the regulated output voltage. 20. The voltage regulator of claim 19, wherein the control stage comprises: a summing block configured to generate an error voltage based on the reference voltage and the regulated output voltage;a steady-state control block configured to control the duty-cycle of the PWM signal based on the error voltage; anda transient control block configured to phase shift the PWM signal based on the error voltage and the inferred slope of the unmeasured current.
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