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A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator la

A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

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1. A silicon-on-insulator semiconductor device, comprising: a first integrated circuit layer on a substrate;an insulator disposed on the substrate;a patterned conductor layer disposed on the insulator and isolated from the substrate; anda second integrated circuit layer disposed on the insulator and

1. A silicon-on-insulator semiconductor device, comprising: a first integrated circuit layer on a substrate;an insulator disposed on the substrate;a patterned conductor layer disposed on the insulator and isolated from the substrate; anda second integrated circuit layer disposed on the insulator and the patterned conductor layer, wherein the patterned conductor layer includes a plurality of biasing portions respectively formed in a plurality of recesses in the insulator. 2. The silicon-on-insulator semiconductor device of claim 1, wherein the patterned conductor is operable to adjustably bias a solid state switch positioned in the second integrated circuit layer. 3. The silicon-on-insulator semiconductor device of claim 1, wherein the plurality of biasing portions are configured to provide a localized bias to a region of the second integrated circuit layer independent of a bias applied to the substrate. 4. The silicon-on-insulator semiconductor device of claim 1, wherein at least one of the plurality of biasing portions is electrically isolated from another one of the plurality of biasing portions. 5. A silicon-on-insulator semiconductor device, comprising: an insulator abutting a substrate;a patterned conductor disposed within the insulator that is electrically insulated from the substrate and coupled to a voltage source, wherein the patterned conductor layer includes a plurality of biasing portions respectively formed in a plurality of recesses in the insulator;an integrated circuit layer disposed on the insulator and the patterned conductor, wherein the voltage source is configured to provide a localized bias voltage; anda solid state switch formed in the integrated circuit layer, wherein the patterned conductor couples the localized bias voltage to the solid state switch. 6. The silicon-on-insulator semiconductor device of claim 5, wherein the patterned conductor comprises polysilicon. 7. The silicon-on-insulator semiconductor device of claim 5, wherein the insulator includes a buried oxide configured to electrically isolate the patterned conductor from the substrate. 8. The silicon-on-insulator semiconductor device of claim 5, wherein the solid state switch includes a base portion positioned on the patterned conductor. 9. The silicon-on-insulator semiconductor device of claim 8, wherein the base portion is coupled to the patterned conductor. 10. The silicon-on-insulator semiconductor device of claim 8, wherein the base portion comprises a doped silicon base. 11. The silicon-on-insulator semiconductor device of claim 10, wherein the doped silicon base is doped with a P-type dopant. 12. A silicon-on-insulator semiconductor device, comprising: an insulator in contact with a substrate;a recess formed in the insulator;a patterned biasing conductor positioned in the recess that is electrically isolated from the substrate, wherein the patterned biasing conductor includes a plurality of biasing portions respectively formed in a plurality of recesses in the insulator;an integrated circuit layer disposed on the insulator and the patterned biasing conductor; anda solid state switch formed in the integrated circuit layer, wherein the patterned biasing conductor is coupled to a base portion of the solid state switch. 13. The silicon-on-insulator semiconductor device of claim 12, wherein the substrate includes monocrystalline silicon that is doped with a p-type dopant. 14. The silicon-on-insulator semiconductor device of claim 12, wherein the biasing conductor includes polysilicon. 15. The silicon-on-insulator semiconductor device of claim 12, wherein the substrate includes an integrated circuit structure that includes at least one of a memory array or a logic circuit. 16. The silicon-on-insulator semiconductor device of claim 15, wherein the memory array comprises a DRAM (dynamic random access memory) array. 17. A silicon-on-insulator semiconductor structure, comprising: an insulator disposed on a substrate configured to be maintained at a selected potential;a patterned biasing conductor positioned in a recess formed in the insulator, wherein the patterned biasing conductor includes a plurality of biasing portions respectively formed in a plurality of recesses in the insulator;an integrated circuit layer disposed on the insulator and the patterned biasing conductor; anda solid state switch formed in the integrated circuit layer, wherein the patterned biasing conductor is coupled to the solid state switch. 18. The silicon-on-insulator semiconductor structure of claim 17, wherein the solid state switch includes a transistor having a base portion positioned on the biasing conductor. 19. The silicon-on-insulator semiconductor structure of claim 18, wherein the base portion of the transistor is electrically coupled to the biasing conductor. 20. The silicon-on-insulator semiconductor structure of claim 17, wherein the biasing conductor includes patterned polysilicon.