Time-gap defect detection apparatus and method
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/00
G06F-013/00
G06K-005/04
G06F-011/00
H04L-012/56
출원번호
US-0358606
(2012-01-26)
등록번호
US-8645591
(2014-02-04)
발명자
/ 주소
Adams, Phillip M.
출원인 / 주소
AFTG-TG, LLC
대리인 / 주소
Pate Baird, PLLC
인용정보
피인용 횟수 :
0인용 특허 :
17
초록▼
A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module
A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.
대표청구항▼
1. A method for detecting time-gap defects in an I/O controller, the method comprising: identifying an I/O controller comprising an internal buffer;enabling the internal buffer;providing a first pattern of data for receiving into the internal buffer;sending to the I/O controller a command effective
1. A method for detecting time-gap defects in an I/O controller, the method comprising: identifying an I/O controller comprising an internal buffer;enabling the internal buffer;providing a first pattern of data for receiving into the internal buffer;sending to the I/O controller a command effective to perform a data transfer of the first pattern and to activate the internal buffer;beginning, by the I/O controller, the data transfer;identifying a last portion of the first pattern within the data transfer;determining a specified quantity corresponding to a time period of delay;delaying, by the specified quantity, a plurality of bytes in the last portion of the first pattern in the data transfer performed by the I/O controller; andrecording an actual pattern reflecting actual operation of the I/O controller's data transfer. 2. The method of claim 1, wherein the I/O controller is selected from a physical device, a software executable, and a signal, operating as an I/O controller. 3. The method of claim 2, wherein the I/O controller is selected from the group consisting of a hardware I/O controller, a virtual I/O controller, an emulated I/O controller, and a simulated I/O controller. 4. The method of claim 1, wherein the I/O controller comprises at least one of a floppy diskette controller, a serial device I/O controller, a parallel device I/O controller, a hard disk I/O controller, an optical disk I/O controller, a network I/O controller, a memory device I/O controller, a protocol I/O controller, and an embedded I/O controller. 5. The method of claim 1, wherein recording further comprises at least one of downloading first information corresponding to the I/O controller, comparing the first information with second information corresponding to the I/O controller's specifications, and downloading third information corresponding to the proper status of the I/O controller's error flags. 6. The method of claim 1, wherein the internal buffer is a FIFO. 7. The method of claim 1, wherein the enabling further comprises configuring the internal buffer with a limiting capacity. 8. The method of claim 1, wherein the I/O controller comprises at least one of a physical circuit, an executable instruction, and a combination thereof containing I/O control information. 9. The method of claim 8, wherein the I/O controller further comprises at least one of a hardware circuit operating to provide I/O control, a virtual device comprising executable instructions providing I/O control, an emulation providing I/O control, and a simulation providing I/O control. 10. The method of claim 9, wherein the I/O controller is selected from the group consisting of a floppy diskette controller, a serial device I/O controller, a parallel device I/O controller, a hard disk I/O controller, an optical disk I/O controller, a network I/O controller, a memory device I/O controller, a protocol I/O controller, and an embedded I/O controller. 11. The method of claim 10, wherein recording further comprises at least one of downloading first information corresponding to the I/O controller, comparing the first information with second information corresponding to the I/O controller's specifications, and downloading third information corresponding to the proper status of the I/O controller's error flags. 12. The method of claim 11, wherein the internal buffer is a FIFO. 13. The method of claim 12, wherein the enabling further comprises configuring the internal buffer with a limiting capacity. 14. A computer readable medium storing executables, the executables comprising: first executables effective to enable an internal buffer of an I/O controller;a first pattern comprising data storable in the internal buffer;second executables effective to command the I/O controller to perform a data transfer of the first pattern with respect to the internal buffer;third executables effective to identify a last portion of data the first pattern in the data transfer performed by the I/O controller;fourth executables effective to delay, by a specified amount, a plurality of bytes in the last portion; andfifth executables effective to receive a resulting pattern reflecting a condition corresponding to the I/O controller's operation with respect to the data transfer. 15. The computer readable medium of claim 14, further comprising at least one of a physical memory device, a virtual memory device, an emulated memory device, and a simulated memory device. 16. The computer readable medium of claim 15, further configured to operably communicate with the I/O controller, wherein the I/O controller is configured as at least one of a physical I/O controller, a virtual I/O controller, an emulated I/O controller, and a simulated I/O controller. 17. The computer readable medium of claim 16, further configured to operably connect to the I/O controller, wherein the I/O controller is at least one of a floppy diskette controller, a serial device I/O controller, a parallel device I/O controller, a hard disk I/O controller, an optical disk I/O controller, a network I/O controller, a memory device I/O controller, a protocol I/O controller, and an embedded I/O controller. 18. The computer readable medium of claim 17, wherein the receiving further comprises at least one of receiving condition data reflecting operation actually performed by the I/O controller, comparing the condition data with the I/O controller's specifications, and determining the proper status of the I/O controller's error flags in view of the condition data. 19. The computer readable medium of claim 18, wherein the enabling comprises configuring the internal buffer with a limiting capacity. 20. The computer readable medium of claim 14, wherein the receiving further comprises at least one of receiving condition data reflecting operation actually performed by the I/O controller, comparing the condition data with the I/O controller's specifications, and determining the proper status of the I/O controller's error flags in view of the condition data. 21. The computer readable medium of claim 14, wherein the enabling comprises configuring the internal buffer with a limiting capacity. 22. A system comprising: a computer readable medium storing data structures, comprising operational data and executables, the executables data structures comprising first executables effective to enable an internal buffer of an I/O controller;a first pattern passing in at least one direction of into and out of the internal buffer;second executables effective to command the I/O controller to perform a data transfer of the first pattern with respect to the internal buffer;third executables effective to identify a last portion of data the first pattern in the data transfer performed by the I/O controller;fourth executables effective to delay, by a specified amount, a plurality of bytes in the last portion; andfifth executables effective to receive a result resulting pattern reflecting a condition corresponding to the I/O controller's operation with respect to the data transfer. 23. The system of claim 22, wherein the computer readable medium comprises at least one of a physical memory device, a virtual memory device, an emulated memory device, and a simulated memory device. 24. The system of claim 23, further comprising: the I/O controller, operably connected to the computer readable medium and configured as at least one of a physical I/O controller, a virtual I/O controller, an emulated I/O controller, and a simulated I/O controller. 25. The system of claim 24, wherein the I/O controller is configured to operate as at least one of a floppy diskette controller, a serial device I/O controller, a parallel device I/O controller, a hard disk I/O controller, an optical disk I/O controller, a network I/O controller, a memory device I/O controller, a protocol I/O controller, and an embedded I/O controller. 26. The system of claim 25, wherein the fifth executable is configured to do at least one of: receiving condition data reflecting operation actually performed by the I/O controller, comparing the condition data with the I/O controller's specifications; and determining the proper status of the I/O controller's error flags in view of the condition data. 27. The system of claim 26, wherein the first executable is programmed to be effective to configure the internal buffer with a limiting capacity.
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