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Methods of forming interconnects in a semiconductor structure

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/4763
출원번호 US-0401566 (2009-03-10)
등록번호 US-8647982 (2014-02-11)
발명자 / 주소
  • Akram, Salman
  • Wark, James M.
  • Hiatt, William M.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    TraskBritt
인용정보 피인용 횟수 : 0  인용 특허 : 31

초록

A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor subs

대표청구항

1. A method of forming an interconnect in a semiconductor structure, comprising: removing a portion of a semiconductor substrate to form a via at least partially extending therethrough, the semiconductor substrate having at least one metal structure comprising aluminum or copper disposed thereon;dep

이 특허에 인용된 특허 (31)

  1. Dean, Timothy B.; Lytle, William H., Activation plate for electroless and immersion plating of integrated circuits.
  2. Rauno Verner Rantanen FI, Apparatus for coating a moving web with at least two coat layers.
  3. Sinha, Nishant, Constructions comprising solder bumps.
  4. Tench, D. Morgan; Warren, Jr., Leslie F.; White, John T., Controlled plating on reactive metals.
  5. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY), Electroless deposition for IC fabrication.
  6. Vratny ; Frederick, Electroless deposition of nickel on aluminum.
  7. Bengston Jon E. (Newington CT), Electroless plating of nickel onto surfaces such as copper or fused tungston.
  8. Suehiro Mitsuo,JPX ; Osawa Satoshi,JPX ; Kikuchi Shunichi,JPX, I/O pin having solder dam for connecting substrates.
  9. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  10. Warren M. Farnworth ; Mike Hess ; David R. Hembree ; James M. Wark ; John O. Jacobson ; Salman Akram, Interconnect for testing semiconductor components having support members for preventing component flexure.
  11. Gaul Stephen Joseph, Intergrated circuit with coaxial isolation and method.
  12. Donges William E., Method and apparatus for dispensing liquid material.
  13. Farnworth, Warren M.; Wood, Alan G.; Hembree, David R., Method for fabricating semiconductor components and interconnects with contacts on opposing sides.
  14. Gaul Stephen Joseph (Melbourne FL), Method of bonding wafers having vias including conductive material.
  15. Lin, Charles W. C., Method of connecting a conductive trace and an insulative base to a semiconductor chip.
  16. Gaul Stephen J. (Melbourne FL), Method of fabrication of surface mountable integrated circuits.
  17. Dong, Cha Deok, Method of forming an isolation layer in a semiconductor devices.
  18. Takase Yoshihisa,JPX ; Okazaki Naoki,JPX, Method of forming electric pad of semiconductor device and method of forming solder bump.
  19. Jiang, Tongbi, Method of making electrical interconnection for attachment to a substrate.
  20. Michal Edith Gross, Plated through hole interconnections.
  21. Brandenburger Jrgen (Selb DEX), Process for electrolessly depositing nickel.
  22. Mack ; Robert L., Process for manufacturing printed circuit boards.
  23. Akram,Salman; Wark,James M.; Hiatt,William M., Selective nickel plating of aluminum, copper, and tungsten structures.
  24. Lindgren, Joseph T., Selective passivation of exposed silicon.
  25. Sergey D. Lopatin ; Carl J. Galewski, Semiconductor catalytic layer and atomic layer deposition thereof.
  26. Miyazawa, Ikuya; Ikehara, Tadayoshi, Semiconductor device and a method of manufacturing the same, a circuit board and an electronic apparatus.
  27. Toshiaki Hasegawa JP; Hajime Nakayama JP, Semiconductor device having a low dielectric layer as an interlayer insulating layer.
  28. Lin Kwang-Lung,TWX ; Lee Chwan-Ying,TWX, Solder bump fabricated method incorporate with electroless deposit and dip solder.
  29. Gaul Stephen J. (Melbourne FL), Surface mountable integrated circuit with conductive vias.
  30. Gaul Stephen Joseph (Melbourne FL), System for interconnecting stacked integrated circuits.
  31. Chang Jieh-Ting,TWX ; Shen Yun-Hung,TWX ; Ke Chih-Ming,TWX, Zincate catalysis electroless metal deposition for via metal interconnection.
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