Methods of forming interconnects in a semiconductor structure
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/44
H01L-021/4763
출원번호
US-0401566
(2009-03-10)
등록번호
US-8647982
(2014-02-11)
발명자
/ 주소
Akram, Salman
Wark, James M.
Hiatt, William M.
출원인 / 주소
Micron Technology, Inc.
대리인 / 주소
TraskBritt
인용정보
피인용 횟수 :
0인용 특허 :
31
초록▼
A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor subs
A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.
대표청구항▼
1. A method of forming an interconnect in a semiconductor structure, comprising: removing a portion of a semiconductor substrate to form a via at least partially extending therethrough, the semiconductor substrate having at least one metal structure comprising aluminum or copper disposed thereon;dep
1. A method of forming an interconnect in a semiconductor structure, comprising: removing a portion of a semiconductor substrate to form a via at least partially extending therethrough, the semiconductor substrate having at least one metal structure comprising aluminum or copper disposed thereon;depositing tungsten over surfaces exposed within the via;selectively forming nickel over the aluminum or copper of the at least one metal structure without forming nickel over the tungsten within the via;activating the tungsten to nickel plating; andforming nickel over an exposed surface of the tungsten. 2. The method of claim 1, further comprising filling the remaining portions of the via with solder. 3. The method of claim 1, further comprising depositing at least one of an oxide material and an adhesion material over surfaces exposed within the via before depositing the tungsten. 4. The method of claim 1, wherein depositing tungsten over surfaces exposed within the via comprises lining the surfaces exposed within the via with the tungsten. 5. The method of claim 1, wherein depositing tungsten over surfaces exposed within the via comprises depositing tungsten over surfaces of at least one bond pad, an oxide material, and the semiconductor substrate exposed within the via. 6. The method of claim 1, wherein selectively forming nickel over the aluminum or copper of the at least one metal structure comprises: activating the aluminum or copper of the at least one metal structure toward metal plating without activating the tungsten; andexposing the aluminum or copper of the at least one metal structure to a nickel plating solution. 7. The method of claim 6, wherein the at least one metal structure comprising aluminum or copper comprises aluminum, and wherein activating the aluminum or copper of the at least one metal structure toward metal plating without activating the tungsten comprises activating the aluminum by exposing the semiconductor structure to a solution comprising zinc. 8. The method of claim 1, wherein forming nickel over the exposed surface of the tungsten comprises exposing the exposed surface of the tungsten to a nickel plating solution. 9. The method of claim 1, further comprising exposing the at least one metal structure to an aqueous solution comprising sodium hydroxide and at least one of nitric acid and phosphoric acid. 10. The method of claim 1, further comprising exposing the tungsten to an aqueous potassium hydroxide solution. 11. The method of claim 1, wherein activating the tungsten to nickel plating comprises exposing the exposed surface of the tungsten to an aqueous solution comprising palladium(II) ions. 12. A method of forming an interconnect in a semiconductor structure, comprising: depositing tungsten over an oxide material lining surfaces within a via extending at least partially through a semiconductor substrate;depositing nickel onto at least one bond pad on the semiconductor substrate without depositing nickel on the tungsten within the via, the at least one bond pad comprising at least one of aluminum and copper;activating the tungsten toward nickel plating;depositing nickel onto the tungsten; andfilling the via with at least one conductive material to form an interconnect. 13. The method of claim 12, wherein depositing tungsten over an oxide material lining surfaces within a via extending at least partially through a semiconductor substrate comprises depositing the tungsten on a titanium nitride material overlying the oxide material. 14. The method of claim 12, wherein the at least one bond pad comprises aluminum, and wherein depositing nickel onto at least one bond pad without depositing nickel on the tungsten within the via comprises: exposing the semiconductor structure to a zincate solution to activate the aluminum without activating the tungsten; andexposing the semiconductor structure to a nickel plating solution. 15. The method of claim 12, wherein depositing nickel onto the tungsten comprises: exposing the semiconductor structure to a solution comprising palladium(II) ions to activate the tungsten; andexposing the semiconductor structure to a nickel plating solution. 16. The method of claim 12, further comprising exposing the tungsten to a potassium hydroxide solution before activating the tungsten toward nickel plating. 17. The method of claim 12, further comprising removing a portion of the semiconductor substrate from a backside of the semiconductor structure to expose the via. 18. A method of forming an interconnect in a semiconductor structure, comprising: removing portions of each of a bond pad comprising at least one of aluminum and copper and a semiconductor substrate to form a via extending through the bond pad and at least partially into the semiconductor substrate;depositing an oxide material over surfaces exposed within the via;depositing tungsten over the oxide material;contacting the bond pad with a nickel plating solution to deposit nickel over the bond pad without depositing nickel over the tungsten;activating the tungsten toward nickel plating;contacting the activated tungsten with a nickel plating solution to deposit nickel over the activated tungsten; andfilling the via with a conductive material to form an interconnect. 19. The method of claim 18, wherein removing portions of each of a bond pad and a semiconductor substrate to form a via extending through the bond pad and at least partially into the semiconductor substrate comprises removing portions of an aluminum bond pad. 20. The method of claim 19, further comprising exposing the semiconductor structure to a solution comprising a zincate solution to activate the aluminum bond pad before contacting the aluminum bond pad with a nickel plating solution to deposit nickel over the aluminum bond pad. 21. The method of claim 18, further comprising exposing the semiconductor structure to a solution comprising at least one of a zinc oxide and Zn(OH)4 before contacting the bond pad with a nickel plating solution to deposit nickel over the bond pad. 22. The method of claim 18, wherein contacting the bond pad with a nickel plating solution to deposit nickel over the bond pad comprises plating portions of the bond pad exposed through a passivation material.
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이 특허에 인용된 특허 (31)
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Farnworth, Warren M.; Wood, Alan G.; Hembree, David R., Method for fabricating semiconductor components and interconnects with contacts on opposing sides.
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