Active area bonding compatible high current structures
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/44
출원번호
US-0717942
(2012-12-18)
등록번호
US-8652960
(2014-02-18)
발명자
/ 주소
Gasner, John T.
Church, Michael D.
Parab, Sameer D.
Bakeman, Jr., Paul E.
Decrosta, David A.
Lomenick, Robert
McCarty, Chris A.
출원인 / 주소
Intersil Americas Inc.
대리인 / 주소
Fogg & Powers LLC
인용정보
피인용 횟수 :
0인용 특허 :
28
초록▼
A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to
A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.
대표청구항▼
1. A method of forming a semiconductor structure, the method comprising: forming one or more intermediate metal layers above a substrate;forming a top metal layer above the one or more intermediate metal layers, wherein the one or more intermediate metal layers and the top metal layer are separated
1. A method of forming a semiconductor structure, the method comprising: forming one or more intermediate metal layers above a substrate;forming a top metal layer above the one or more intermediate metal layers, wherein the one or more intermediate metal layers and the top metal layer are separated from each other with insulating layers, wherein each of the insulating layers is formed above a respective one of the one or more intermediate metal layers;forming a bond pad in a portion of the top metal layer;forming a passivation layer over the top metal layer;patterning the passivation layer to expose a surface of the bond pad;forming one or more conductor lines underlying the bond pad from portions of at least one of the one or more intermediate metal layers;wherein one of the insulating layers between the bond pad and a closest underlying conductor line is formed to have a thickness that resists formation of cracks in the one of the insulating layers due to vertical and horizontal stresses on the semiconductor structure. 2. The method of claim 1, wherein the thickness of the one of the insulating layers between the bond pad and the closest underlying conductor line is at least 1.5 microns. 3. The method of claim 1, further comprising forming a sub-layer between the bond pad and the closest underlying conductor line, the material of the sub-layer being relatively stiff compared to the bond pad. 4. The method of claim 3, wherein the sub-layer is formed to comprise a nitride layer. 5. The method of claim 3, wherein the sub-layer comprises an insulator layer. 6. The method of claim 1, further comprising forming one or more gaps between portions of at least one of the one or more conductor lines under the bond pad. 7. A method of forming a semiconductor structure, the method comprising: forming one or more intermediate metal layers above a substrate;forming one or more insulation layers, each of the one or more insulation layers formed above a respective one of the one or more intermediate metal layers;forming a top metal layer above the one or more insulation layers, wherein each of the one or more insulation layers separates the respective one or more intermediate metal layers and the top metal layer from each other;forming a bond pad in a portion of the top metal layer;forming a passivation layer over the top metal layer;patterning the passivation layer to expose a surface of the bond pad;forming one or more conductor lines underlying the bond pad from portions of at least one of the one or more intermediate metal layers; andforming a sub-layer of material between the bond pad and the closest underlying conductor line;wherein the sub-layer of material is configured to distribute stresses over an insulation layer of the one or more insulation layers that is located between the bond pad and the closest underlying conductor line to reduce cracking in the insulation layer that is located between the bond pad and the closest underlying conductor line. 8. The method of claim 7, wherein the sub-layer of material comprises a nitride layer. 9. The method of claim 7, further comprising forming the sub-layer of material to extend over an area at least as large as the area under the bond pad. 10. A method of forming a packaged semiconductor, the method comprising: forming one or more intermediate metal layers above a substrate;forming one or more insulation layers, each of the one or more insulation layers formed above a respective one of the one or more intermediate metal layers;forming a top metal layer above the one or more intermediate metal layers, wherein the one or more intermediate metal layers and the top metal layer are separated from each other with a respective one of the one or more insulation layers formed above each of the one or more intermediate metal layers;forming a bond pad in a portion of the top metal layer;forming a passivation layer over the top metal layer;patterning the passivation layer to expose a surface of the bond pad;forming one or more conductor lines underlying the bond pad from portions of at least one of the one or more intermediate metal layers;attaching an electrical connection of a package terminal to the bond pad of the semiconductor structure; andenclosing the semiconductor structure in a package;wherein one of the one or more insulation layers between the bond pad and a nearest underlying conductor line is formed to have a thickness that resists formation of cracks in one of the one or more insulation layers due to stresses caused by at least one of attachment of the electrical connection to the bond pad or temperature excursions. 11. The method of claim 10, further comprising forming the one of the one or more insulation layers between the bond pad and the nearest underlying conductor line to have a thickness of at least 1.5 microns. 12. The method of claim 10, further comprising forming a sub-layer of material between the bond pad and the nearest underlying conductor line. 13. The method of claim 12, wherein the sub-layer of material is configured to distribute stresses over the one of the one or more insulation layers between the bond pad and the nearest underlying conductor line to reduce cracking in the one of the one or more insulation layers between the bond pad and the nearest underlying conductor line. 14. The method of claim 12, wherein the sub-layer of material extends to cover an area at least as large as the area under the bond pad. 15. A method of forming a packaged semiconductor, the method comprising: attaching an electrical connection of a package terminal to a bond pad of a semiconductor structure comprising one or more intermediate metal layers above a substrate, insulating layers, wherein each of the insulating layers formed above a respective one of the one or more intermediate metal layers; a top metal layer above the one or more intermediate metal layers and the insulating layers, the bond pad formed from a portion of the top metal layer, and a passivation layer over the top metal layer; the passivation layer patterned to expose a surface of the bond pad; andenclosing the semiconductor structure in the package;wherein one of the insulating layers between the bond pad and a first underlying conductor line has a thickness that resists formation of cracks in the one of the insulating layers due to stresses caused by at least one of attachment of the electrical connection to the bond pad or temperature excursions, wherein the first underlying conductor line is formed from portions of one of the intermediate metal layers underlying the bond pad and is located adjacent to the one of the insulating layers that is between the bond pad and the first underlying conductor line. 16. The method of claim 15, wherein the the one of the insulating layers between the bond pad and the first underlying conductor line has a thickness of at least 1.5 microns. 17. The method of claim 15, wherein the semiconductor structure includes a sub-layer of material between the bond pad and the first underlying conductor line. 18. The method of claim 17, wherein the sub-layer of material is configured to distribute stresses over the one of the insulating layers between the bond pad and the first underlying conductor line to reduce cracking in the one of the insulating layers between the bond pad and the first underlying conductor line. 19. The method of claim 17, wherein the sub-layer of material extends to cover an area at least as large as the area under the bond pad.
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이 특허에 인용된 특허 (28)
Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
Gasner, John T.; Church, Michael D.; Parab, Sameer D.; Bakeman, Jr., Paul E.; Decrosta, David A.; Lomenick, Robert; McCarty, Chris A., Active area bonding compatible high current structures.
Gasner,John T.; Church,Michael D.; Parab,Sameer D.; Bakeman, Jr.,Paul E.; Decrosta,David A.; Lomenick,Robert L.; McCarty,Chris A., Active area bonding compatible high current structures.
Gasner,John T; Church,Michael D; Parab,Sameer D; Bakeman, Jr.,Paul E; Decrosta,David A; Lomenic,Robert; McCarty,Chris A, Active area bonding compatible high current structures.
Sutardja,Sehat; Wu,Albert; Lee,Jin Yuan; Lin,Mou Shiung, Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits.
John J. Ellis-Monaghan ; Paul M. Feeney ; Robert M. Geffken ; Howard S. Landis ; Rosemary A. Previti-Kelly ; Bette L. Bergman Reuter ; Matthew J. Rutten ; Anthony K. Stamper ; Sally J. Yankee, Method and structure of column interconnect.
Tanaka Kazuo,JPX, Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal.
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