초록 ▼

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS mem

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

대표청구항 ▼

1. An integrated circuit structure comprising: a first substrate comprising a first surface supporting interconnect contacts;a substantially flexible semiconductor second substrate comprising a first surface and a second surface at least one of which supports interconnect contacts, wherein the secon

1. An integrated circuit structure comprising: a first substrate comprising a first surface supporting interconnect contacts;a substantially flexible semiconductor second substrate comprising a first surface and a second surface at least one of which supports interconnect contacts, wherein the second surface is opposite the first surface, is formed by removing semiconductor material from the second substrate, and is smoothed or polished after removal of the semiconductor material;conductive paths between the interconnect contacts supported by the first surface of the first substrate and the interconnect contacts supported by the second substrate; wherein the first substrate and the second substrate overlap fully or partially in a stacked relationship; andwherein at least one of:i.) the first and second substrates are bonded together in fixed relationship to one another at least predominantly with metal, or at least predominantly with silicon- based dielectric material and metal; andii.) the integrated circuit structure further comprises a low-stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 2. The integrated circuit structure of claim 1, further comprising a plurality of integrated circuit devices formed on the second substrate, the plurality of integrated circuit devices defining an integrated circuit die having an area; wherein the second substrate is formed from a semiconductor wafter and extends throughout and is of one piece throughout at least a substantial portion of the area of the integrated circuit die. 3. The integrated circuit structure of claim 2, wherein the second substrate comprises one of a thinned monocrystalline semiconductor substrate and a thin polysilicon semiconductor substrate. 4. The integrated circuit structure of claim 2, wherein the integrated circuit die comprises one of active circuitry and passive circuitry. 5. The integrated circuit structure of claim 2, wherein integrated circuit die comprises both active circuitry and passive circuitry. 6. The integrated circuit structure of claim 2, further comprising circuitry formed on the first substrate. 7. The integrated circuit structure of claim 2, further comprising: at least one additional thin substrate having circuitry formed thereon; a first one of the said at least one additional thinned substrate being bonded to the second substrate and any additional ones of the at least one additional thinned substrates being bonded to a directly adjacent one of the at least one additional thinned substrate; and conductive paths formed between the first one of the at least one additional thinned substrate and at least one of the first and second substrates and also between each of any additional ones of the at least one additional thinned substrate and at least one of the substrates of the integrated circuit structure. 8. The integrated circuit structure of claim 2, wherein the first substrate is a non-semiconductor material. 9. The integrated circuit structure of claim 2, wherein the integrated circuit die comprises redundant circuitry. 10. The integrated circuit structure of claim 2, wherein at least two of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant. 11. The integrated circuit structure of claim 2, wherein at least three of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant. 12. The integrated circuit structure of claim 1, wherein the first and second substrates are bonded by at least one diffusion bond. 13. The integrated circuit structure of claim 1, comprising at least one conductive path that passes through semiconductor material of the second substrate and is insulated by an insulating material that passes through the semiconductor material of the second substrate. 14. The integrated circuit structure of claim 13, comprising a plurality of conductive paths that pass through semiconductor material of the second substrate, wherein at least one of the plurality of conductive paths is redundant. 15. The integrated circuit structure of claim 1, wherein the second substrate is formed from a semiconductor wafer. 16. The integrated circuit structure of claim 1, further comprising a low stress silicon-based dielectric layer formed on the smoothed or polished surface and having a stress of 5×108 dynes/cm2 tensile or less. 17. An integrated circuit structure comprising: a first substrate having topside and bottomside surfaces, wherein the topside surface of the first substrate supports interconnect contacts; a substantially flexible semiconductor second substrate having topside and bottom-side surfaces, wherein at least one of the topside surface and the bottom-side surface of the second substrate supports interconnect contacts, and wherein the bottom-side surface of the second substrate is formed by removing semiconductor material from the second substrate and is smoothed or polished after removal of the semiconductor material; and conductive paths between the interconnect contacts supported by the topside surface of the first substrate and the interconnect contacts supported by the second substrate; wherein the first substrate and the second substrate overlap fully or partially in a stacked relationship; and wherein at least one of: i.) the first and second substrates are bonded together in fixed relationship to one another at least predominantly with metal, or at least predominantly with silicon- based dielectric material and metal; andii.) the integrated circuit structure further comprises a low-stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 18. The integrated circuit structure of claim 17, comprising a plurality of integrated circuit devices formed on the second substrate, the plurality of integrated circuit devices defining an integrated circuit die having an area; wherein the second substrate is formed from a semiconductor wafer and extends throughout and is of one piece throughout at least a substantial portion of the area of the integrated circuit die. 19. The integrated circuit structure of claim 18, wherein selected ones of said interconnect contacts supported by said topside surface of said first substrate are in electrical contact with selected ones of the interconnect contacts supported by said bottom-side surface of said second substrate so as to form said electrical connections. 20. The integrated circuit structure of claim 18, further comprising: at least one additional thin substrate having circuitry formed thereon; a first of the at least one additional thinned substrate being bonded to the second substrate and any additional ones of the at least one additional thinned substrate being bonded to a directly adjacent one of the at least one additional thinned substrate; and conductive paths formed between the first one of the at least one additional thinned substrate and at least one of the first and second substrates and also between each of any additional ones of the at least one additional thinned substrate and at least one of said substrates of the integrated circuit structure. 21. The integrated circuit structure of claim 18, wherein the first substrate and the second substrate are the same size or overlap each other completely. 22. The integrated circuit structure of claim 18, wherein at least one of the first and second substrates comprises a low stress dielectric layer, wherein the low stress dielectric layer is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about 5×108 dynes/cm2 tensile or less. 23. The integrated circuit structure of claim 18, further comprising memory circuitry on the second substrate, wherein a portion of the memory circuitry is redundant memory circuitry. 24. The integrated circuit structure of claim 18, wherein the integrated circuit die comprises redundant circuitry. 25. The integrated circuit structure of claim 18, wherein at least two of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less; a plurality of polysilicon layers are provided with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the first substrate and the second substrate; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon- based dielectric layer. 26. The integrated circuit structure of claim 18, wherein at least three of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less; a plurality of polysilicon layers are provided with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the first substrate and the second substrate; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer. 27. The integrated circuit structure of claim 17, wherein the first and second substrates are bonded by at least one diffusion bond. 28. The integrated circuit structure of claim 17, comprising at least one conductive path that passes through semiconductor material of the second substrate and is insulated by an insulating material that passes through the semiconductor material of the second substrate. 29. The integrated circuit structure of claim 28, comprising at least one conductive path that is redundant. 30. The integrated circuit structure of claim 17, wherein the second substrate is formed from a semiconductor wafer. 31. The integrated circuit structure of claim 17, further comprising a low stress silicon-based dielectric layer formed on the smoothed or polished surface and having a stress of 5×108 dynes/cm2 dynes/cm2 tensile or less. 32. The integrated circuit structure of claim 17, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the first substrate and the second substrate. 33. The integrated circuit structure of claim 17, further comprising a plurality of integrated circuits in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer. 34. The integrated circuit structure of claim 17, further comprising a plurality of integrated circuits in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer. 35. The stacked integrated circuit of claim 17, wherein the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations. 36. The stacked integrated circuit of claim 35, comprising at least one conductive interconnection that passes vertically through the substantially flexible semiconductor substrate and is insulated from the substantially flexible semiconductor substrate by a low stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 37. The integrated circuit structure of claim 35, wherein the first substrate and the second substrate are formed with one of single crystal semiconductor material and polysilicon semiconductor material. 38. The integrated circuit structure of claim 35, wherein one of the first substrate and the second substrate is formed using a different process technology than another of the first substrate and the second substrate, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance. 39. The integrated circuit structure of claim 35, comprising a logic layer including the first substrate and a memory layer including the second substrate, wherein the logic layer performs testing of the memory layer. 40. The integrated circuit structure of claim 35, comprising a memory layer including the second substrate, wherein the memory layer has multiple memory locations having at least one memory location used for sparing, wherein data from the at least one memory location on the memory layer is used instead of data from a defective memory location on the memory layer. 41. The integrated circuit structure of claim 35, comprising a logic layer including the first substrate and a memory layer including the second substrate, wherein the logic layer performs programmable gate line address assignment with respect to the memory layer. 42. The integrated circuit structure of claim 35, comprising circuitry formed on the first substrate and on the second substrate, wherein information processing is performed on data routed between the circuitry on the first and second substrates. 43. The integrated circuit structure of claim 35, wherein at least one of the first and second substrates comprises reconfiguration circuitry. 44. The integrated circuit structure of claim 35, wherein at least one of the first and second substrates comprises logic for performing at least one of the following functions: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing. 45. The integrated circuit structure of claim 35, the first substrate and the second substrate together further comprising: a memory array including a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines; circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells. 46. The integrated circuit structure of claim 35, wherein the first substrate and the second substrate together comprise a logic layer comprising a controller and a memory layer, the logic layer and the memory layer together further comprising: a plurality of data lines and a plurality of gate lines on each of the at least one memory layer; an array of memory cells on each of the at least one memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines; a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines. 47. The integrated circuit structure of claim 46, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 48. The integrated circuit structure of claim 17, the plurality of substrates together further comprising: a memory array including a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines; circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells. 49. An integrated circuit structure comprising: a first substrate having a first and second surface; a semiconductor second substrate having a first and second surface, wherein said second surfaces of the first and second substrates are opposite to said first surfaces; wherein at least one of the first substrate and the second substrate is thinned and substantially flexible, thereby providing at least one thinned substrate, and wherein the second surface of the at least one thinned substrate is formed by removing semiconductor material from the second substrate and is smoothed or polished after removal of the semiconductor material; conductive paths between at least two of: a contact layer formed over the first surface of the first substrate, a contact layer formed over the first surface of the second substrate, and a contact layer formed over the second surface of the second substrate; wherein the first substrate and the second substrate overlap fully or partially in a stacked relationship; and wherein at least one of: i.) the first and second substrates are bonded together in fixed relationship with one another at least predominantly with metal, or at least predominantly with silicon-based dielectric material and metal; andii.) the integrated circuit structure further comprises a low-stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 50. The integrated circuit structure of claim 49, comprising a plurality of integrated circuit devices formed on the second substrate, the plurality of integrated circuit devices defining an integrated circuit die having an area; wherein the second substrate is formed from a semiconductor wafer and extends throughout and is of one piece throughout at least a substantial portion of the area of the integrated circuit die. 51. The integrated circuit structure of claim 50, wherein the first substrate and the second substrate are the same size or overlap each other completely. 52. The integrated circuit structure of claim 50, wherein at least one of the first and second substrates comprises a low stress dielectric layer, wherein the low stress dielectric layer is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a stress of about 5×108 dynes/cm2 tensile or less. 53. The integrated circuit structure of claim 50, further comprising memory circuitry on the second substrate, wherein a portion of the memory circuitry is redundant memory circuitry. 54. The integrated circuit structure of claim 50, wherein at least two of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bondat least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less; a plurality of polysilicon layers are provided with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the first substrate and the second substrate; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer. 55. The integrated circuit structure of claim 50, wherein at least three of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less; a plurality of polysilicon layers are provided with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the first substrate and the second substrate; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer. 56. The integrated circuit structure of claim 50, wherein the integrated circuit die comprises redundant circuitry. 57. The integrated circuit structure of claim 49, wherein the first and second substrates are bonded by at least one diffusion bond. 58. The integrated circuit structure of claim 49, comprising at least one conductive path that passes through semiconductor material of the second substrate and is insulated by an insulating material that passes through the semiconductor material of the second substrate. 59. The integrated circuit structure of claim 58, comprising at least one conductive path that is redundant. 60. The integrated circuit structure of claim 49, wherein the substrate is formed from a semiconductor wafer. 61. The integrated circuit structure of claim 49, further comprising a low stress silicon-based dielectric layer formed on the smoothed or polished surface and having a stress of 5×108 dynes/cm2 tensile or less. 62. The integrated circuit structure of claim 49, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the first substrate and the second substrate. 63. The integrated circuit structure of claim 49, further comprising a plurality of integrated circuits in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer. 64. The integrated circuit structure of claim 49, further comprising a plurality of integrated circuits in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer. 65. The integrated circuit structure of claim 49, comprising circuitry formed on the first substrate and on the second substrate, wherein information processing is performed on data routed between the circuitry on the first and second substrates. 66. The integrated circuit structure of claim 49, wherein at least one of the first and second substrates comprises reconfiguration circuitry. 67. The integrated circuit structure of claim 49, wherein at least one of the first and second substrates comprises logic for performing at least one of the following functions: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing. 68. The integrated circuit structure of claim 49, the first substrate and the second substrate together further comprising: a memory array including a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines; circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells. 69. The integrated circuit structure of claim 49, wherein the first substrate and the second substrate together comprise a logic layer comprising a controller and a memory layer, the logic layer and the memory layer together further comprising: a plurality of data lines and a plurality of gate lines on each of the at least one memory layer; an array of memory cells on each of the at least one memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines; a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines. 70. The integrated circuit structure of claim 69, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 71. The stacked integrated circuit of claim 49, wherein the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations. 72. The stacked integrated circuit of claim 71, comprising at least one conductive interconnection that passes vertically through the substantially flexible semiconductor substrate and is insulated from the substantially flexible semiconductor substrate by a low stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 73. The integrated circuit structure of claim 71, wherein the first substrate and the second substrate are formed with one of single crystal semiconductor material and polysilicon semiconductor material. 74. The integrated circuit structure of claim 71, wherein one of the first substrate and the second substrate is formed using a different process technology than another of the first substrate and the second substrate, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance. 75. The integrated circuit structure of claim 71, comprising a logic layer including the first substrate and a memory layer including the second substrate, wherein the logic layer performs testing of the memory layer. 76. The integrated circuit structure of claim 71, comprising a memory layer including the second substrate, wherein the memory layer has multiple memory locations having at least one memory location used for sparing, wherein data from the at least one memory location on the memory layer is used instead of data from a defective memory location on the memory layer. 77. The integrated circuit structure of claim 71, comprising a logic layer including the first substrate and a memory layer including the second substrate, wherein the logic layer performs programmable gate line address assignment with respect to the memory layer. 78. The integrated circuit structure of claim 71, comprising circuitry formed on the first substrate and on the second substrate, wherein information processing is performed on data routed between the circuitry on the first and second substrates. 79. The integrated circuit structure of claim 71, wherein at least one of the first and second substrates comprises reconfiguration circuitry. 80. The integrated circuit structure of claim 71, wherein at least one of the first and second substrates comprises logic for performing at least one of the following functions: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing. 81. The integrated circuit structure of claim 71, the first substrate and the second substrate together further comprising: a memory array including a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines; circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells. 82. The integrated circuit structure of claim 81, wherein the first substrate and the second substrate together comprise a logic layer comprising a controller and a memory layer, the logic layer and the memory layer together further comprising: a plurality of data lines and a plurality of gate lines on each of the at least one memory layer; an array of memory cells on each of the at least one memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines; a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines. 83. The integrated circuit structure of claim 82, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 84. An integrated circuit structure comprising: a plurality of substrates having first and second surfaces and arranged in a stacked relationship, wherein at least one of the substrates is a substantially flexible semiconductor substrate having one or more integrated circuits formed on the first surface and a second surface that is formed by removal of semiconductor material and that is smoothed or polished after removal of the semiconductor material; and at least one interconnection between two of the plurality of substrates; wherein one of the plurality of substrates and the substantially flexible semiconductor substrate overlap fully or partially in a stacked relationship; and wherein at least one of: i.) said two of the plurality of substrates are bonded together in fixed relationship to one another at least predominantly with metal, or at least predominantly with silicon-based dielectric material and metal; andii.) the integrated circuit structure further comprises a low-stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 85. The integrated circuit structure of claim 50, wherein at least one conductive path passes through at least one of the plurality of substrates and the conductive path is insulated by an insulating material from said substrate. 86. The integrated circuit structure of claim 85, comprising at least one conductive path that is redundant. 87. The integrated circuit structure of claim 84, comprising a plurality of integrated circuit devices formed on the second substrate, the plurality of integrated circuit devices defining an integrated circuit die having an area; wherein the second substrate is formed from a semiconductor wafer and extends throughout and is of one piece throughout at least a substantial portion of the area of the integrated circuit die. 88. The integrated circuit structure of claim 87, wherein the integrated circuit die comprises redundant circuitry. 89. The integrated circuit structure of claim 87, wherein at least two of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; the plurality of substrates form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less; a plurality of polysilicon layers are provided with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the plurality of substrates; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer. 90. The integrated circuit structure of claim 87, wherein at least three of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; the plurality of substrates form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less; a plurality of polysilicon layers are provided with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the plurality of substrates; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer; a plurality of integrated circuits are provided in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer. 91. The integrated circuit structure of claim 84, wherein the first and second substrates are bonded by at least one diffusion bond. 92. The integrated circuit structure of claim 84, wherein the second substrate is formed from a semiconductor wafer. 93. The integrated circuit structure of claim 84, further comprising a low stress silicon-based dielectric layer formed on the smoothed or polished surface and having a stress of 5×108 dynes/cm2 tensile or less. 94. The integrated circuit structure of claim 84, further comprising a plurality of polysilicon layers with at least one low stress silicon-based dielectric layer deposited on each of said polysilicon layers in a stacked relationship to at least one of the plurality of substrates. 95. The integrated circuit structure of claim 84, further comprising a plurality of integrated circuits in a stacked relationship each of said plurality of integrated circuits comprising a polysilicon substrate and at least one low stress silicon-based dielectric layer. 96. The integrated circuit structure of claim 84, further comprising a plurality of integrated circuits in a stacked relationship each of said plurality of integrated circuits comprising a deposited polysilicon layer and at least one low stress silicon-based dielectric layer. 97. The integrated circuit structure of claim 84, comprising circuitry formed on the plurality of substrates, wherein information processing is performed on data routed between the circuitry on the plurality of substrates. 98. The integrated circuit structure of claim 84, wherein at least one of the plurality of substrates comprises reconfiguration circuitry. 99. The integrated circuit structure of claim 84, wherein at least one of the plurality of substrates comprises logic for performing at least one of the following functions: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing. 100. The integrated circuit structure of claim 84, wherein the plurality of substrates together comprise a logic layer comprising a controller and a memory layer, the logic layer and the memory layer together further comprising: a plurality of data lines and a plurality of gate lines on each of the at least one memory layer; an array of memory cells on each of the at least one memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines; a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines. 101. The integrated circuit structure of claim 100, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 102. The stacked integrated circuit of claim 84, wherein the plurality of substrates form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations. 103. The stacked integrated circuit of claim 102, comprising at least one conductive interconnection that passes vertically through the substantially flexible semiconductor substrate and is insulated from the substantially flexible semiconductor substrate by a low stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 104. The integrated circuit structure of claim 102, wherein the first substrate and the second substrate are formed with one of single crystal semiconductor material and polysilicon semiconductor material. 105. The integrated circuit structure of claim 102, wherein one of the first substrate and the second substrate is formed using a different process technology than another of the first substrate and the second substrate, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance. 106. The integrated circuit structure of claim 102, comprising a logic layer including the first substrate and a memory layer including the second substrate, wherein the logic layer performs testing of the memory layer. 107. The integrated circuit structure of claim 102, comprising a memory layer including the second substrate, wherein the memory layer has multiple memory locations having at least one memory location used for sparing, wherein data from the at least one memory location on the memory layer is used instead of data from a defective memory location on the memory layer. 108. The integrated circuit structure of claim 102, comprising a logic layer including the first substrate and a memory layer including the second substrate, wherein the logic layer performs programmable gate line address assignment with respect to the memory layer. 109. The integrated circuit structure of claim 102, comprising circuitry formed on the first substrate and on the second substrate, wherein information processing is performed on data routed between the circuitry on the first and second substrates. 110. The integrated circuit structure of claim 102, wherein at least one of the first and second substrates comprises reconfiguration circuitry. 111. The integrated circuit structure of claim 102, wherein at least one of the first and second substrates comprises logic for performing at least one of the following functions: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing. 112. The integrated circuit structure of claim 102, the first substrate and the second substrate together further comprising: a memory array including a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines; circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells. 113. The integrated circuit structure of claim 102, wherein the first substrate and the second substrate together comprise a logic layer comprising a controller and a memory layer, the logic layer and the memory layer together further comprising: a plurality of data lines and a plurality of gate lines on each of the at least one memory layer; an array of memory cells on each of the at least one memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines; a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines. 114. The integrated circuit structure of claim 113, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines. 115. An integrated circuit structure comprising: a first substrate comprising a first surface supporting interconnect contacts;a substantially flexible semiconductor second substrate comprising a first surface and a second surface at least one of which supports interconnect contacts, wherein the second surface is opposite the first surface and wherein the second surface of the second substrate is formed by removal of semiconductor material from the second substrate and is smoothed or polished after removal of the semiconductor material;conductive paths between the interconnect contacts supported by the first surface of the first substrate and of the interconnect contacts supported by the second substrate;wherein the first substrate and the second substrate overlap fully or partially in a stacked relationship; andthe first and second substrates are bonded together in fixed relationship to one another at least predominantly with metal, or at least predominantly with silicon-based dielectric material and metal. 116. The integrated circuit structure of claim 115, further comprising a plurality of integrated circuit devices formed on the second substrate, the plurality of integrated circuit devices defining an integrated circuit die having an area; wherein the second substrate is formed from a semiconductor wafer and extends throughout and is of one piece throughout at least a substantial portion of the area of the integrated circuit die. 117. The integrated circuit structure of claim 116, further comprising a low-stress dielectric material on and supported by the second substrate, but not extending beyond the area of the integrated circuit die, and having a stress of 5×108 dynes/cm2 tensile or less. 118. The integrated circuit structure of claim 117, wherein the second substrate comprises a monocrystalline semiconductor substrate and the semiconductor material that is removed is monocrystalline semiconductor material and is removed to thin the monocrystalline semiconductor substrate. 119. The integrated circuit structure 116, wherein the conductive paths comprise: vertical interconnect conductors extending vertically through the second substrate; andvertical dielectric insulators extending vertically through the second substrate and around the interconnect conductors and having a stress of about 5×108 dynes/cm2 tensile or less. 120. The integrated circuit structure of claim 119, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 121. The integrated circuit structure of claim 115, wherein at least two of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less. 122. The integrated circuit structure of claim 115, wherein at least three of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less. 123. The integrated circuit structure of claim 115, wherein the second substrate defines a die, extends throughout and is of one piece throughout at least a substantial portion of the die, and is formed from a semiconductor wafer. 124. The integrated circuit structure of claim 123, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 125. The integrated circuit structure of claim 123, wherein the second substrate comprises a monocrystalline semiconductor substrate and the semiconductor material that is removed is monocrystalline semiconductor material and is removed to thin the monocrystalline semiconductor substrate. 126. The integrated circuit structure of claim 123, wherein the conductive paths comprise: vertical interconnect conductors extending vertically through the second substrate; andvertical dielectric insulators extending vertically through the second substrate and around the interconnect conductors and having a stress of about 5×108 dynes/cm2 tensile or less. 127. The integrated circuit structure of claim 126, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 128. The integrated circuit structure of claim 115, further comprising a low stress silicon-based dielectric layer formed on the smoothed or polished surface and having a stress of 5×108 dynes/cm2 tensile or less. 129. An integrated circuit structure comprising: a first substrate comprising a first surface supporting interconnect contacts;a substantially flexible semiconductor second substrate comprising a first surface and a second surface at least one of which supports interconnect contacts, wherein the second surface is opposite the first surface and wherein the second surface of the second substrate is formed by removal of semiconductor material from the second substrate and is smoothed or polished after removal of the semiconductor material; andconductive paths between the interconnect contacts supported by the first surface of the first substrate and of the interconnect contacts supported by the second substrate;wherein the first substrate and the second substrate overlap fully or partially in a stacked relationship; andwherein the integrated circuit structure further comprises a low-stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 130. The integrated circuit structure of claim 129, further comprising a plurality of integrated circuit devices formed on the second substrate, the plurality of integrated circuit devices defining an integrated circuit die having an area; wherein the second substrate is formed from a semiconductor wafer and extends throughout and is of one piece throughout at least a substantial portion of the area of the integrated circuit die. 131. The integrated circuit structure of claim 130, further comprising a low-stress dielectric material on and supported by the second substrate, but not extending beyond the area of the integrated circuit die, and having a stress of 5×108 dynes/cm2 tensile or less. 132. The integrated circuit structure of claim 131, wherein the second substrate comprises a monocrystalline semiconductor substrate and the semiconductor material that is removed is monocrystalline semiconductor material and is removed to thin the monocrystalline semiconductor substrate. 133. The integrated circuit structure of claim 130, wherein the conductive paths comprise: vertical interconnect conductors extending vertically through the second substrate; andvertical dielectric insulators extending vertically through the second substrate and around the interconnect conductors and having a stress of about 5×108 dynes/cm2 tensile or less. 134. The integrated circuit structure of claim 133, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 135. The integrated circuit structure of claim 129, wherein at least two of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less. 136. The integrated circuit structure of claim 129, wherein at least three of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less. 137. The integrated circuit structure of claim 129, wherein the second substrate defines a die, extends throughout and is of one piece throughout at least a substantial portion of the die, and is formed from a semiconductor wafer. 138. The integrated circuit structure of claim 137, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 139. The integrated circuit structure of claim 137, wherein the second substrate comprises a monocrystalline semiconductor substrate and the semiconductor material that is removed is monocrystalline semiconductor material and is removed to thin the monocrystalline semiconductor substrate. 140. The integrated circuit structure of claim 137, wherein the conductive paths comprise: vertical interconnect conductors extending vertically through the second substrate; andvertical dielectric insulators extending vertically through the second substrate and around the interconnect conductors and having a stress of about 5×108 dynes/cm2 tensile or less. 141. The integrated circuit structure of claim 140, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 142. The integrated circuit structure of claim 129, further comprising a low stress silicon-based dielectric layer formed on the smoothed or polished surface and having a stress of 5×108 dynes/cm2 tensile or less. 143. An integrated circuit structure comprising: a first substrate comprising a first surface supporting interconnect contacts;a substantially flexible semiconductor second substrate comprising a first surface and a second surface at least one of which supports interconnect contacts, wherein the second surface is opposite the first surface and wherein the second surface of the second substrate is formed by removing semiconductor material from the second substrate and is smoothed or polished after removal of the semiconductor material; andconductive paths between the interconnect contacts supported by the first surface of the first substrate and of the interconnect contacts supported by the second substrate;wherein the first substrate and the second substrate overlap fully or partially in a stacked relationship. 144. The integrated circuit structure of claim 143, further comprising a plurality of integrated circuit devices formed on the second substrate, the plurality of integrated circuit devices defining an integrated circuit die having an area; wherein the second substrate is formed from a semiconductor wafer and extends throughout and is of one piece throughout at least a substantial portion of the area of the integrated circuit die. 145. The integrated circuit structure of claim 144, further comprising a low-stress dielectric material on and supported by the second substrate, but not extending beyond the area of the integrated circuit die, and having a stress of 5×108 dynes/cm2 tensile or less. 146. The integrated circuit structure of claim 145, wherein the second substrate comprises a monocrystalline semiconductor substrate and the semiconductor material that is removed is monocrystalline semiconductor material and is removed to thin the monocrystalline semiconductor substrate. 147. The integrated circuit structure of claim 144, wherein the conductive paths comprise: vertical interconnect conductors extending vertically through the second substrate; andvertical dielectric insulators extending vertically through the second substrate and around the interconnect conductors and having a stress of about 5×108 dynes/cm2 tensile or less. 148. The integrated circuit structure of claim 147, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 149. The integrated circuit structure of claim 143, wherein at least two of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less. 150. The integrated circuit structure of claim 143, wherein at least three of: the first substrate is a non-semiconductor material; at least one of said surfaces of the second substrate has formed thereon a dielectric with a stress of about 5×108 dynes/cm2 tensile or less; the dielectric is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; the second substrate has microprocessor circuitry formed thereon; the second substrate has reconfiguration circuitry formed thereon; the second substrate has redundant circuitry formed thereon; the second substrate has a thickness of about 1 to 8 microns; the second substrate has a thickness of about 10 microns or less; the layers formed over the first substrate and the second substrate are bonded by at least one diffusion bond; at least one conductive path passes through the first substrate between the first surface and the second surface of the first substrate; at least one conductive path passes through the second substrate between the first surface and the second surface of the second substrate; conductive paths are formed between and within overlapping portions of bonded surfaces of the layers formed over the first substrate and second substrate; the second surface of the second substrate has an oxide layer formed thereon; at least one conductive path passes through at least one of the first substrate and the second substrate and the conductive path is insulated by an insulating material from said substrate; at least one of the integrated circuits comprises redundant circuitry; at least one of the conductive paths is redundant; the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations; a low stress silicon-based dielectric layer is formed on the smoothed or polished surface having a stress of 5×108 dynes/cm2 tensile or less. 151. The integrated circuit structure of claim 143, wherein the second substrate defines a die, extends throughout and is of one piece throughout at least a substantial portion of the die, and is formed from a semiconductor wafer. 152. The integrated circuit structure of claim 151, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 153. The integrated circuit structure of claim 151, wherein the second substrate comprises a monocrystalline semiconductor substrate and the semiconductor material that is removed is monocrystalline semiconductor material and is removed to thin the monocrystalline semiconductor substrate. 154. The integrated circuit structure of claim 151, wherein the conductive paths comprise: vertical interconnect conductors extending vertically through the second substrate; andvertical dielectric insulators extending vertically through the second substrate and around the interconnect conductors and having a stress of about 5×108 dynes/cm2 tensile or less. 155. The integrated circuit structure of claim 154, further comprising a low-stress dielectric material formed on and supported by the second substrate, but not extending beyond the die, and having a stress of 5×108 dynes/cm2 tensile or less. 156. The integrated circuit structure of claim 143, further comprising a low stress silicon-based dielectric layer formed on the smoothed or polished surface and having a stress of 5×108 dynes/cm2 tensile or less. 157. The stacked integrated circuit of claim 143, wherein the first substrate and the second substrate form a stacked integrated memory circuit, wherein at least a portion of the stacked integrated memory circuit is partitioned into a plurality of vertically interconnected circuit blocks, wherein a plurality of said circuit blocks can independently perform memory operations. 158. The stacked integrated circuit of claim 157, comprising at least one conductive interconnection that passes vertically through the substantially flexible semiconductor substrate and is insulated from the substantially flexible semiconductor substrate by a low stress silicon-based dielectric material having a stress of 5×108 dynes/cm2 tensile or less. 159. The integrated circuit structure of claim 157, wherein the first substrate and the second substrate are formed with one of single crystal semiconductor material and polysilicon semiconductor material. 160. The integrated circuit structure of claim 157, wherein one of the first substrate and the second substrate is formed using a different process technology than another of the first substrate and the second substrate, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance. 161. The integrated circuit structure of claim 157, comprising a logic layer including the first substrate and a memory layer including the second substrate, wherein the logic layer performs testing of the memory layer. 162. The integrated circuit structure of claim 157, comprising a memory layer including the second substrate, wherein the memory layer has multiple memory locations having at least one memory location used for sparing, wherein data from the at least one memory location on the memory layer is used instead of data from a defective memory location on the memory layer. 163. The integrated circuit structure of claim 157, comprising a logic layer including the first substrate and a memory layer including the second substrate, wherein the logic layer performs programmable gate line address assignment with respect to the memory layer. 164. The integrated circuit structure of claim 157, comprising circuitry formed on the first substrate and on the second substrate, wherein information processing is performed on data routed between the circuitry on the first and second substrates. 165. The integrated circuit structure of claim 157, wherein at least one of the first and second substrates comprises reconfiguration circuitry. 166. The integrated circuit structure of claim 157, wherein at least one of the first and second substrates comprises logic for performing at least one of the following functions: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing. 167. The integrated circuit structure of claim 157, the first substrate and the second substrate together further comprising: a memory array including a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines; circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells. 168. The integrated circuit structure of claim 157, wherein the first substrate and the second substrate together comprise a logic layer comprising a controller and a memory layer, the logic layer and the memory layer together further comprising: a plurality of data lines and a plurality of gate lines on each of the at least one memory layer; an array of memory cells on each of the at least one memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines; a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines. 169. The integrated circuit structure of claim 167, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.