$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Low temperature P+ polycrystalline silicon material for non-volatile memory device

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/112
  • H01L-021/82
  • H01L-021/20
  • H01L-029/04
  • H01L-029/06
  • H01L-029/10
출원번호 US-0452657 (2012-04-20)
등록번호 US-8658476 (2014-02-25)
발명자 / 주소
  • Sun, Xin
  • Jo, Sung Hyun
  • Kumar, Tanmay
출원인 / 주소
  • Crossbar, Inc.
대리인 / 주소
    Ogawa P.C.
인용정보 피인용 횟수 : 57  인용 특허 : 90

초록

A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrysta

대표청구항

1. A method of forming a non-volatile memory device, comprising: providing a substrate having a surface region;forming a first dielectric material overlying the surface region of the substrate;forming a first electrode structure overlying the first dielectric material;forming a polycrystalline silic

이 특허에 인용된 특허 (90)

  1. Bandyopadhyay, Abhijit; Hou, Kun; Maxwell, Steven, 3D polysilicon diode with low contact resistance and method for forming same.
  2. Krieger,Juri Heinrich; Yudanov,Nikolay Fedorovich, Active programming and operation of a memory device.
  3. Chien, Wei-Chih; Chang, Kuo-Pin; Chen, Yi-Chou; Lai, Erh-Kun; Hsieh, Kuang-Yeu, Aluminum copper oxide based memory devices and methods for manufacture.
  4. Owen Alan E. (Edinburgh GB6) Snell Anthony J. (Penicuik GB6) Hajto Janos (Edinburgh GB6) Lecomber Peter G. (Dundee GB6) Rose Mervyn J. (Forfar GB6), Amorphous silicon memory.
  5. Li, Tingkai; Hsu, Sheng Teng; Evans, David R., Back-to-back metal/semiconductor/metal (MSM) Schottky diode.
  6. Schricker, April Dawn; Sekar, Deepak C.; Fu, Andy; Clark, Mark, Damascene process for carbon memory element with MIIM diode.
  7. Chevallier,Christophe; Rinerson,Darrell, Discharge of conductive array lines in fast memory.
  8. Kishimoto Yoshio (Hirakata JPX) Suzuki Masaaki (Hirakata JPX), Electrically reprogrammable nonvolatile memory device.
  9. Elkins, Patricia C.; Moore, John T.; Klein, Rita J., Electroless plating of metal caps for chalcogenide-based memory devices.
  10. Kau, Derchang; Kalb, Johannes; Karpov, Elijah; Spadini, Gianpaolo, Energy-efficient set write of phase change memory with switch.
  11. Kumar, Tanmay; Herner, S. Brad, Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride.
  12. Kumar, Tanmay; Herner, S. Brad, Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride.
  13. Chang Kuang-Yeh,TWX, High density ROM and a method of making the same.
  14. Scheuerlein,Roy E; Petti,Christopher J, High density contact to relaxed geometry layers.
  15. Wendell P. Noble ; Leonard Forbes, Highly conductive composite polysilicon gate for CMOS integrated circuits.
  16. Ovshinsky Stanford R. (2700 Squirrel Rd. Bloomfield Hills MI 48013) Hudgens Stephen J. (2 Alexandria Towne Southfield MI 48075) Strand David A. (2091 Daintree West Bloomfield MI 48323) Czubatyj Wolod, Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memo.
  17. Nirschl, Thomas; Kakoschke, Ronald, Integrated circuit having dielectric layer including nanocrystals.
  18. Gogl,Dietmar; Viehmann,Hans Heinrich, Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module.
  19. Freeman Richard D. (San Carlos CA) Linoff Joseph D. (San Jose CA) Saxe Timothy (Los Altos CA), Logic cell and routing architecture in a field programmable gate array.
  20. Hosotani, Keiji; Asao, Yoshiaki; Nitayama, Akihiro, Magnetic random access memory and method of manufacturing the same.
  21. Wolstenholme Graham R. ; Gonzalez Fernando ; Zahorik Russell C., Memory cell incorporating a chalcogenide element and method of making same.
  22. Schricker, April; Herner, Brad; Clark, Mark, Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same.
  23. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  24. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  25. Krieger, Juri H.; Yudanoy, Nikolai, Memory device.
  26. Krieger,Juri Heinrich; Yudanov,Nikolay Fedorovich, Memory device.
  27. Happ,Thomas; Pinnow,Cay Uwe; Kund,Michael, Memory device electrode with a surface structure.
  28. Lung, Hsiang-Lan, Memory device having wide area phase change element and small electrode contact area.
  29. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active and passive layers.
  30. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active passive layers.
  31. Bertin, Claude L.; Huang, X. M. Henry; Rueckes, Thomas; Sivarajan, Ramesh, Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks.
  32. Forouhi Abdul R. (San Jose CA) Hawley Frank W. (Campbell CA) McCollum John L. (Saratoga CA) Yen Yeouchung (San Jose CA), Metal-to-metal antifuse with conductive.
  33. Mills, Jr., Allen P., Method and apparatus for temperature compensation of read-only memory.
  34. Wang,Lien Chang; Diao,Zhitao; Ding,Yunfei, Method and system for providing current balanced writing for memory cells and magnetic devices.
  35. Ohtake, Fumio; Akasaka, Yasushi; Murakoshi, Atsushi; Suguro, Kyoichi, Method for fabricating semiconductor device having gate electrode with polymetal structure of polycrystalline silicon film and metal film.
  36. Kawamata Ikuo (Tokyo JPX), Method for making semiconductor device having improved thermal stress characteristics.
  37. Pinnow, Cay-Uwe; Ufert, Klaus-Dieter, Method for manufacturing an integrated circuit including an electrolyte material layer.
  38. Oguro Shizuo (Tokyo JPX), Method of fabricating a polycrystalline silicon film having a reduced resistivity.
  39. Ji-Wei Liou TW; Chih-Jen Huang TW; Pao-Chuan Lin TW, Method of fabricating a trenched flash memory cell.
  40. Gilton,Terry L., Method of manufacture of programmable conductor memory.
  41. Gilton, Terry L., Method of manufacture of programmable switching circuits and memory cells employing a glass layer.
  42. Pruijmboom Armand ; Jansen Alexander C. L.,NLX ; Koster Ronald,NLX ; Van Der Wel Willem,NLX, Method of manufacturing a semiconductor device with a BiCMOS circuit.
  43. Kramer Niels,NLX ; Niesten Maarten J. H.,NLX ; Lodders Wilhelmus H. M.,NLX ; Oversluizen Gerrit,NLX, Method of operating a programmable, non-volatile memory device.
  44. Gaun,David; Spitzer,Stuart; Yudanov,Nicolay F, Method to improve yield and simplify operation of polymer memory cells.
  45. Dunton,Samuel V.; Herner,S. Brad, Method to minimize formation of recess at surface planarized by chemical mechanical planarization.
  46. Kumar, Pragati; Barstow, Sean; Shanker, Sunil; Chiang, Tony, Methods for forming resistive switching memory elements by heating deposited layers.
  47. Kuekes Philip J. ; Williams R. Stanley ; Heath James R., Molecular wire crossbar memory.
  48. Liu, Jun, Multi-level programmable PCRAM memory.
  49. Shannon John M.,GBX, Multiple memory element semiconductor memory devices.
  50. Saito Takeshi (Tokyo JPX), Non-linear device for driving liquid crystal display.
  51. Owen Alan E. (Edinburgh GB6) Sarrabayrouse Gerard (Tolouse FRX) LeComber Peter G. (Dundee GB6) Spear Walter E. (Dundee GB6), Non-volatile amorphous semiconductor memory device utilizing a forming voltage.
  52. Schloss, Lawrence; Meyer, Rene; Kinney, Wayne; Lambertson, Roy; Brewer, Julie Casperson, Non-volatile memory device ion barrier.
  53. Brubaker, Matthew D.; Paz de Araujo, Carlos A.; Celinska, Jolanta, Non-volatile resistance switching memories and methods of making same.
  54. Raghuram, Usha; Herner, S. Brad, Nonvolatile phase change memory cell having a reduced contact area.
  55. Scheuerlein, Roy E., Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse.
  56. Herner, Scott Brad, On/off ratio for non-volatile memory device and method.
  57. Harshfield,Steven T.; Wright,David Q., PCRAM memory cell and method of making same.
  58. Karpov, Ilya V.; Kuo, Charles C.; Kim, Yudong; Pellizzer, Fabio, Phase change memory with damascene memory element.
  59. Gaun,David; Krieger,Juri H; Spitzer,Stuart, Polymer memory cell operation.
  60. Wolstenholme Graham R. ; Ireland Philip J., Polysilicon pillar diode for use in a non-volatile memory cell.
  61. Venkatasamy, Venkatram; Sun, Ming; Setiadi, Dadi, Programmable resistive memory cell with sacrificial metal.
  62. Sur ; Jr. Harlan Lee ; Bothra Subhas, Programmable semiconductor structures and methods for making the same.
  63. Liu, Jun, Reproducible resistance variable insulating memory devices having a shaped bottom electrode.
  64. Toda, Haruki; Kubo, Koichi, Resistance change memory device.
  65. Muraoka, Shunsaku; Osano, Koichi; Fujii, Satoru, Resistance variable element and resistance variable memory apparatus.
  66. Campbell,Kristy A., Resistance variable memory with temperature tolerant materials.
  67. Rose Mervyn J. (Angus GBX) Hajto Janos (Edinburgh GBX) Owen Alan E. (Edinburgh GBX) Osborne Ian S. (Dundee GBX) Snell Anthony J. (Midlothian GBX) Le Comber ; deceased Peter G. (late of Dundee GBX by , Resistive memory element.
  68. Chen, Yiran; Li, Hai; Zhu, Wenzhong; Wang, Xiaobin; Huang, Henry; Liu, Hongyue, Resistive sense memory calibration for self-reference read method.
  69. Phatak, Prashant; Chiang, Tony; Miller, Michael; Wu, Wen, Resistive switching memory element including doped silicon electrode.
  70. Kumar, Pragati; Malhotra, Sandra G.; Barstow, Sean; Chiang, Tony, Resistive-switching nonvolatile memory elements.
  71. Kerns,Kevin J.; Peng,Zhishi, SPICE optimized for arrays.
  72. Kinoshita, Kentaro; Yoshida, Chikako, Semiconductor device and manufacturing method of the same.
  73. Matsunaga, Noriaki; Shimooka, Yoshiaki; Nakamura, Naofumi, Semiconductor device and method for manufacturing semiconductor device.
  74. Yamazaki, Shunpei; Ohnuma, Hideto; Takano, Tamae; Ohtani, Hisashi, Semiconductor device and method of fabricating the same.
  75. Petti, Christopher J.; Herner, S. Brad, Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide.
  76. Eichman Eric C. (Phoenix AZ) Salt Thomas C. (Chandler AZ), Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method ther.
  77. Eichman Eric C. ; Salt Thomas C., Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method ther.
  78. Yongjun Hu ; Pai-Hung Pan ; Er-Xuan Ping ; Randhir P. S. Thakur ; Scott DeBoer, Semiconductor structure having a doped conductive layer.
  79. Hsu, Sheng Teng, Shared bit line cross-point memory array incorporating P/N junctions.
  80. Maddox ; III Roy L. (Boise ID) Mathews Viju K. (Boise ID) Fazan Pierre C. (Boise ID), Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of.
  81. Katti, Romney R.; Zhu, Theodore, Spintronic devices with integrated transistors.
  82. Katti, Romney R.; Zhu, Theodore, Spintronic devices with integrated transistors.
  83. Hosomi, Masanori; Ohmori, Hiroyuki; Ikarashi, Minoru; Yamamoto, Tetsuya; Higo, Yutaka; Yamane, Kazutaka; Oishi, Yuki; Kano, Hiroshi, Storage element and memory.
  84. Scheuerlein, Roy E., Structure and method for biasing phase change memory array for reliable writing.
  85. Scheuerlein, Roy E., Structure and method for biasing phase change memory array for reliable writing.
  86. Spitzer,Stuart; Krieger,Juri H; Gaun,David, Systems and methods for adjusting programming thresholds of polymer memory cells.
  87. Kaschmitter James L. (Pleasanton CA), Three dimensional amorphous silicon/microcrystalline silicon solar cells.
  88. Toda, Haruki, Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array.
  89. Canaperi,Donald F.; Dalton,Timothy J.; Gates,Stephen M.; Krishnan,Mahadevaiyer; Nitta,Satya V.; Purushothaman,Sampath; Smith,Sean P. E., Very low effective dielectric constant interconnect Structures and methods for fabricating the same.
  90. Herner, Scott Brad, p+ polysilicon material on aluminum for non-volatile memory device and method.

이 특허를 인용한 특허 (57)

  1. Jo, Sung Hyun, Conductive path in switching material in a resistive random access memory device and control.
  2. Kim, Kuk-Hwan; Lu, Ping; Chen, Chen-Chun; Jo, Sung Hyun, Controlling on-state current for two-terminal memory.
  3. Jo, Sung Hyun; Lu, Wei, Device switching using layered device structure.
  4. Jo, Sung Hyun; Lu, Wei, Device switching using layered device structure.
  5. Jo, Sung Hyun; Lu, Wei, Device switching using layered device structure.
  6. Maxwell, Steven Patrick, Electrode structure for a non-volatile memory device and method.
  7. Asnaashari, Mehdi; Nazarian, Hagop; Nguyen, Sang, Field programmable gate array utilizing two-terminal non-volatile memory.
  8. Nazarian, Hagop; Nguyen, Sang Thanh; Kumar, Tanmay, Field programmable gate array utilizing two-terminal non-volatile memory.
  9. Nazarian, Hagop; Nguyen, Sang Thanh; Kumar, Tanmay, Field programmable gate array utilizing two-terminal non-volatile memory.
  10. Nazarian, Hagop; Jo, Sung Hyun, Filamentary based non-volatile resistive memory device and method.
  11. Nazarian, Hagop; Jo, Sung Hyun, Filamentary based non-volatile resistive memory device and method.
  12. Jo, Sung Hyun, Guided path for forming a conductive filament in RRAM.
  13. Jo, Sung Hyun, Guided path for forming a conductive filament in RRAM.
  14. Jo, Sung Hyun, Hetero-switching layer in a RRAM device and method.
  15. Jo, Sung Hyun, Hetero-switching layer in a RRAM device and method.
  16. Nguyen, Sang; Nazarian, Hagop, High operating speed resistive random access memory.
  17. Nishitani, Yu; Kaneko, Yukihiro; Ueda, Michihito, Learning method of neural network circuit.
  18. Maxwell, Steven Patrick, Line and space architecture for a non-volatile memory device.
  19. Sun, Xin; Jo, Sung Hyun; Kumar, Tanmay, Low temperature P+ polycrystalline silicon material for non-volatile memory device.
  20. Herner, Scott Brad, Low temperature fabrication method for a three-dimensional memory device and structure.
  21. Nazarian, Hagop; Jo, Sung Hyun; Lu, Wei, Memory array architecture with two-terminal memory cells.
  22. Lu, Wei, Method and structure of monolithically integrated IC and resistive memory using IC foundry-compatible processes.
  23. Maxwell, Steven Patrick; Jo, Sung-Hyun, Method for silver deposition for a non-volatile memory device.
  24. Maxwell, Steven Patrick; Jo, Sung-Hyun; Herner, Scott Brad, Method for silver deposition for a non-volatile memory device.
  25. Gee, Harry Yue; Maxwell, Steven Patrick; Vasquez, Jr., Natividad; Clark, Mark Harold, Methods for fabricating resistive memory device switching material using ion implantation.
  26. Lu, Wei, Modeling technique for resistive random access memory (RRAM) cells.
  27. Narayanan, Sundar; Maxwell, Steve; Vasquez, Jr., Natividad; Gee, Harry Yue, Monolithically integrated resistive memory using integrated-circuit foundry compatible processes.
  28. Narayanan, Sundar; Maxwell, Steve; Vasquez, Jr., Natividad; Gee, Harry Yue, Monolithically integrated resistive memory using integrated-circuit foundry compatible processes.
  29. Nishitani, Yu; Kaneko, Yukihiro; Ueda, Michihito, Neural network circuit and learning method thereof.
  30. Jo, Sung Hyun; Kim, Kuk-Hwan; Kumar, Tanmay, Noble metal / non-noble metal electrode for RRAM applications.
  31. Nazarian, Hagop; Nguyen, Sang, Non-volatile memory with overwrite capability and low write amplification.
  32. Herner, Scott Brad, On/off ratio for non-volatile memory device and method.
  33. Herner, Scott Brad, On/off ratio for nonvolatile memory device and method.
  34. Herner, Scott Brad, Pillar structure for memory device and method.
  35. Lu, Wei; Jo, Sung Hyun, Rectified switching of two-terminal memory via real time filament formation.
  36. Maxwell, Steven Patrick; Jo, Sung Hyun, Reduced diffusion in metal electrode for two-terminal memory.
  37. Jo, Sung Hyun; Nazarian, Hagop, Resistive RAM with preferental filament formation region and methods.
  38. Nazarian, Hagop; Kumar, Tanmay; Jo, Sung Hyun, Resistive memory cell with solid state diode.
  39. Jo, Sung Hyun; Kim, Kuk-Hwan; Kumar, Tanmay, Resistive memory device and fabrication methods.
  40. Jo, Sung Hyun; Kim, Kuk-Hwan; Kumar, Tanmay, Resistive memory device and fabrication methods.
  41. Lu, Wei, Resistive memory using SiGe material.
  42. Nazarian, Hagop; Nguyen, Sang, Resistive random access memory equalization and sensing.
  43. Jo, Sung Hyun; Kim, Kuk-Hwan, Resistive random access memory with non-linear current-voltage relationship.
  44. Jo, Sung Hyun, Resistor structure for a non-volatile memory device and method.
  45. Clark, Mark Harold; Vasquez, Natividad; Maxwell, Steven, Scalable RRAM device architecture for a non-volatile memory device and method.
  46. Clark, Mark Harold; Herner, Scott Brad, Seed layer for a p+ silicon germanium material for a non-volatile memory device and method.
  47. Herner, Scott Brad, Silver interconnects for stacked non-volatile memory device and method.
  48. Herner, Scott Brad, Stackable non-volatile resistive switching memory device.
  49. Herner, Scott Brad, Stackable non-volatile resistive switching memory device and method of fabricating the same.
  50. Gee, Harry Yue; Clark, Mark Harold; Maxwell, Steven Patrick; Jo, Sung Hyun; Vasquez, Jr., Natividad, Sub-oxide interface layer for two-terminal memory.
  51. Lu, Wei; Jo, Sung Hyun, Switching device having a non-linear element.
  52. Lu, Wei; Jo, Sung Hyun; Nazarian, Hagop, Switching device having a non-linear element.
  53. Herner, Scott Brad, Thin film transistor steering element for a non-volatile memory device.
  54. Jo, Sung Hyun; Bettinger, Joanna; Liu, Xianliang, Three-dimensional oblique two-terminal memory with enhanced electric field.
  55. Jo, Sung Hyun; Kim, Kuk-Hwan; Bettinger, Joanna, Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects.
  56. Jo, Sung Hyun; Kim, Kuk-Hwan; Bettinger, Joanna, Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects.
  57. Jo, Sung Hyun; Herner, Scott Brad, Two terminal resistive switching device structure and method of fabricating.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트