[특허]Depth-optimal mapping of logic chains in reconfigurable fabrics

Depth-optimal mapping of logic chains in reconfigurable fabrics 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-017/50
출원번호	US-0236781 (2008-09-24)
등록번호	US-8661394 (2014-02-25)
발명자 / 주소	Frederick, Michael T. Somani, Arun K.
출원인 / 주소	Iowa State University Research Foundation, Inc.
대리인 / 주소	McKee, Voorhees & Sease, P.L.C.
인용정보	피인용 횟수 : 0 인용 특허 : 158

초록 ▼

A method of creating logic chains in a Boolean network of a reconfigurable fabric is provided. The method includes creating a plurality of logic chains in the reconfigurable fabric. The plurality of logic chains include at least one arithmetic logic chain and at least one non-arithmetic logic chain. A method of creating logic chains in a Boolean network of a look-up table based FPGA includes: applying a labeling method by (a) finding a depth increasing node, (b) isolating the depth increasing node, and (c) finding minimum height cuts; mapping to generate a mapping solution using the minimum height cuts; applying a duplication method to implement an exclusivity constraint; and arranging connections in the look-up table based FPGA using the logic chains.

대표청구항 ▼

1. A method of creating logic chains in a Boolean network representing a logic circuit and mapping the logic circuit to an electronic circuit, the method comprising: creating a plurality of generic logic chains in the logic circuit with each of the generic logic chains being useable for arithmetic operations or non-arithmetic operations; andmapping the plurality of logic chains in the logic circuit to an electronic circuit;wherein each of the logic chains being a subnetwork of adjacent nodes with equal routing depth and increasing logic depth. 2. The method of claim 1, wherein each of the plurality of logic chains being created in polynomial time. 3. The method of claim 1 wherein each of the plurality of logic chains being created without HDL arithmetic chain macros. 4. The method of claim 1 wherein the creating the plurality of logic chains comprises labeling. 5. The method of claim 4 wherein the labeling further comprises finding a depth increasing node. 6. The method of claim 5 wherein the labeling further comprises isolating the depth increasing node. 7. The method of claim 6 wherein the labeling further comprises finding minimum height cuts. 8. The method of claim 7 wherein the creating the plurality of logic chains further comprises mapping to generate a mapping solution using the minimum height cuts. 9. The method of claim 8 wherein the creating the plurality of logic chains further comprises applying a duplication method to implement an exclusivity constraint. 10. The method of claim 9 wherein the creating the plurality of logic chains further comprises applying a relaxation method to relax routing depth. 11. The method of claim 10 wherein the relaxation method comprises a least critical branch trimming method. 12. The method of claim 1 wherein the reconfigurable fabric is a field programmable gate array (FPGA). 13. A process of creating logic chains in a Boolean network representing a logic circuit, the logic circuit suitable for mapping to an electronic circuit, the process comprising: creating a plurality of generic logic chains with each of the generic logic chains being useable for arithmetic operations or non-arithmetic operations; andwherein each of the logic chains being a sub network of adjacent nodes with equal routing depth and increasing logic depth of the logic circuit. 14. The process of claim 13 further comprising mapping the logic circuit to the electronic circuit. 15. A method of creating logic chains in a Boolean network representing a logic circuit, the logic circuit suitable for mapping to an electronic circuit, the process comprising: creating a plurality of generic logic chains from adjacent cell interconnection structures with each of the generic logic chains being useable for arithmetic operations or non-arithmetic operations;wherein each of the logic chains being a sub network of adjacent nodes with equal routing depth and increasing logic depth of the logic circuit. 16. The method of claim 15 wherein each of the plurality of generic logic chains is associated with a depth increasing node in the logic circuit. 17. The method of claim 15 wherein the mapping is performed without preserving hardware description language (HDL) macros.

이 특허에 인용된 특허 (158)

Goran Bilski, ALU implementation in single PLD logic cell.
상세보기
Koike Hideharu (Yokohama JPX), AND-OR logic circuit including a feedback path.
상세보기
Schwartz Samuel (Saratoga CA), Apparatus and method for composing digital information on a data bus.
상세보기
Stephen L. Wasson, Apparatus and method for interleaving a signal carry chain in an integrated circuit.
상세보기
Stephen L. Wasson, Apparatus and method for programmable datapath arithmetic arrays.
상세보기
Moore Victor S. (Pompano Beach FL) Kraft Wayne R. (Coral Springs FL) Rhodes ; Jr. Joseph C. (Boca Raton FL), Apparatus and method using a programmable logic array for decoding an operation code and providing a plurality of sequen.
상세보기
Simpson John Richard (3 Applecrest Rd. Weston MA 02193), Apparatus for high-speed solution of arbitrary mathematical expressions with logic code generator and programmable logic.
상세보기
Bialas, Jr.,John Stanley; Kilmoyer,Ralph D., Apparatus for performing stuck fault testings within an integrated circuit.
상세보기
Chang Web (39939 Stevenson Common ; V-2133 Fremont CA 94538), Application specific field programmable gate array.
상세보기
Perner Frederick A., Arithmetic cell for field programmable devices.
상세보기
Kondou Harufusa (Hyogo JPX) Ando Hideki (Hyogo JPX), Arithmetic unit with alternate mark inversion (AMI) coding.
상세보기
Morton Steven G. (Oxford CT), Associative array with five arithmetic paths.
상세보기
Fant Karl, Asynchronous register.
상세보기
Pedersen, Bruce, Automated implementation of non-arithmetic operators in an arithmetic logic cell.
상세보기
Moore Victor S. (Pompano Beach FL) Leininger Joel C. (Boca Raton FL), Binary logic structure employing programmable logic arrays and useful in microword generation apparatus.
상세보기
Bazes Mel (Santa Clara CA), Binomially-encoded finite state machine.
상세보기
Lee,Andy L.; Ngo,Ninh; Betz,Vaughn; Lewis,David; Pederson,Bruce; Schleicher,James, Bypass-able carry chain in a programmable logic device.
상세보기
Moy Thomas H. (Allentown PA), CMOS programmable logic array.
상세보기
Hong Se J. (Poughkeepsie NY) Ostapko Daniel L. (Poughkeepsie NY), Changeable decoder structure for a folded logic array.
상세보기
Zlotnick Fredrick (Scottsdale AZ), Circuit and method of configuring a field programmable gate array.
상세보기
Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
상세보기
Kaviani, Alireza S.; Mohan, Sundararajarao; Wittig, Ralph D.; Young, Steven P.; New, Bernard J., Configurable logic block for PLD with logic gate for combining output with another configurable logic block.
상세보기
Freidin Philip M. ; Trimberger Stephen M. ; Mahoney John E. ; Erickson Charles R., Configurable parallel and bit serial load apparatus.
상세보기
Freidin Philip M. ; Trimberger Stephen M. ; Mahoney John E. ; Erickson Charles R., Configurable parallel and bit serial load apparatus.
상세보기
Freidin Philip M. ; Trimberger Stephen M. ; Mahoney John E. ; Erickson Charles R., Configurable parallel and bit serial load apparatus.
상세보기
Freidin Philip M. ; Trimberger Stephen M. ; Mahoney John E. ; Erickson Charles R., Configurable parallel and bit serial load apparatus.
상세보기
Wong Sing Y. (Sunnyvale CA), Current source which saves power in programmable logic array circuitry.
상세보기
Devine William T. (Ulster Park NY) Gianopulos William (West Hurley NY), Demand powered programmable logic array.
상세보기
Steele Randy C. (Folsom CA) Hibdon Gregory B. (Folsom CA) Sturges Jay J. (Orangevale CA) Vireday Richard P. (Cameron Park CA), Deterministic method and an apparatus for minimal switch circuits.
상세보기
Osman, Fazil I., Dynamic re-programmable PLA.
상세보기
O\Hara ; Jr. Almerin C. (Kingston NY), Dynamically reprogrammable array logic system.
상세보기
Mead Carver (Pasadena CA) Shen Cecilia (Palo Alto CA), Electrically erasable programmable logic array (EEPLA).
상세보기
Leijten Nowak,Katarzyna, Electronic circuit with array of programmable logic cells.
상세보기
Nowak Leijten,Katarzyna, Electronic circuit with array of programmable logic cells.
상세보기
Thornber Karvel Kuhn (Berkeley Heights NJ), Electronically alterable diode logic circuit.
상세보기
Graham ; III Hatch (Santa Clara CA) Seltz Daniel (Mountain View CA), Electronically programmable gate array having programmable interconnect lines.
상세보기
Phillips John William ; Saxena Rahul, Exception reporting on function generation in an SIMD processor.
상세보기
Agrawal,Om P.; Sharpe Geisler,Bradley A., FPGA with register-intensive architecture.
상세보기
McCollum John L., Field programmable digital signal processing array integrated circuit.
상세보기
McCollum John L. (Saratoga CA), Field programmable digital signal processing array integrated circuit.
상세보기
Cavlan Napoleone (Cupertino CA), Field-programmable logic device with programmable foldback to control number of logic levels.
상세보기
Cavlan Napoleone (Cupertino CA), Field-programmable logic device with programmable foldback to control number of logic levels.
상세보기
Agrawal Om P. (San Jose CA) Ilgenstein Kerry A. (Austin TX) Wright Michael J. (Santa Clara CA) Moench Jerry D. (Austin TX) Khu Arthur H. (San Mateo CA), Flexible, programmable cell array interconnected by a programmable switch matrix.
상세보기
Cruz Claude A. (Fremont CA) Vermeulen Johannes C. (Longmont CO), Flip-flop programmer using cascaded logic arrays.
상세보기
Moore, Donald W.; Verstraete, Rick A., Functionally redundant logic network architectures.
상세보기
Moore, Donald W.; Verstraete, Rick A., Functionally redundant logic network architectures with logic selection means.
상세보기
Robertson Perry J. ; Witzke Edward L., General purpose programmable accelerator board.
상세보기
Balasubramanian Peruvemba S. (Manassas VA) Greenspan Stephen B. (Reston VA) Venkataraman Krishnamurthi (Manassas VA), Generalized performance power optimized PLA circuits.
상세보기
Cox Dennis T. (Kingston NY) Devine William T. (Ulster Park NY) Kelly Gilbert J. (Red Hook NY), High density logic array.
상세보기
Wang, Hsinshih, High performance datapath unit for behavioral data transmission and reception.
상세보기
Aoki Naoaki ; Takahashi Osamu ; Silberman Joel Abraham ; Dhong Sang Hoo, High speed incrementer with array method.
상세보기
Jigour Robin J. (San Jose CA) Lee Shueh-Mien J. (Sunnyvale CA) Pourkeramati Ali (Santa Clara CA), High-performance programmable logic device.
상세보기
Jigour Robin J. (San Jose CA) Lee Shueh-Mien J. (Sunnyvale CA) Pourkeramati Ali (Santa Clara CA), High-performance user programmable logic device (PLD).
상세보기
Steele Randy C. (Folsom CA) Vireday Richard P. (Cameron Park CA), High-speed comparator logic for wide compares in programmable logic devices.
상세보기
Zapisek John M. (Hauppauge NY) Giulekas Gus (West Hempstead NY), High-speed merged plane logic function array.
상세보기
Zapisek John M. (Hauppauge NY) Giulekas Gus (West Hempstead NY), High-speed merged plane logic function array.
상세보기
Gtze Volkmar (Grafenau DEX) Potz Gnther (Sindelfingen DEX), Highly integrated programmable logic array utilizing AND and OR arrays.
상세보기
Brockmann Werner (Altenbeken DEX), Integrated circuit component.
상세보기
Kondo Tetsujiro,JPX ; Horishi Takashi,JPX, Integrated circuit for processing digital signal.
상세보기
Brice Jean M. (Grenoble FRX), Integrated logic network with simplified programming.
상세보기
Horninger Karlheinrich (Eglharting DT), Integrated programmable logic arrangement.
상세보기
Horninger Karlheinrich (Eglharting DT), Integrated programmable logic array.
상세보기
Hebenstreit Ernst (Munich DT), Integrated, programmable logic arrangement.
상세보기
Kalter Howard L. (Colchester VT) Wiedman Francis W. (Stowe VT), Interlaced programmable logic array having shared elements.
상세보기
Rhodes F. Matthew (Arlington MA) Raffel Jack I. (Lexington MA), Laser programmable integrated circuit.
상세보기
Kaviani, Alireza S., Literal sharing method for fast sum-of-products logic.
상세보기
Kaviani, Alireza S., Literal sharing method for fast sum-of-products logic.
상세보기
Graham Andrew C. (Sunnyvale) France Michael G. (Fremont) Burd Robert C. (Sunnyvale) Fitzpatrick Mark E. (San Jose CA), Logic array having high frequency internal clocking.
상세보기
Williams Robert Russell (Rochester MN), Logic array with enhanced flexibility.
상세보기
Weinberger Arnold (Poughkeepsie NY), Logic array with multiple readout tables.
상세보기
Boppana, Vamsi; Bhattacharya, Debashis, Logic circuit having a functionally redundant transistor network.
상세보기
Cases Moises (Delray Beach FL) Kraft Wayne R. (Coral Springs FL) Moore Victor S. (Deerfield Beach FL) Stahl ; Jr. William L. (Coral Springs FL) Thoma Nandor G. (Boca Raton FL), Logic performing cell for use in array structures.
상세보기
Cases Moises (Delray Beach FL) Kraft Wayne R. (Coral Springs FL) Stahl ; Jr. William L. (Coral Springs FL) Thoma Nandor G. (Boca Raton FL), Logic performing cell for use in array structures.
상세보기
Smith Kent F. (Salt Lake City UT) Carter Tony M. (Salt Lake City UT), Logical circuit array.
상세보기
Gongwer Geoffrey S. (San Jose CA), Low power logic array device.
상세보기
Yum Daniel (Poway CA), Low power partitioned PLA.
상세보기
Yum Daniel (Poway CA), Low power small area PLA.
상세보기
Klink James, Medical identification bracelet.
상세보기
Dancea,Ioan, Method and VLSI circuits allowing to change dynamically the logical behavior.
상세보기
Burke, David, Method and apparatus for executing standard functions in a computer system using a field programmable gate array.
상세보기
New, Bernard J.; Young, Steven P., Method and apparatus for incorporating a multiplier into an FPGA.
상세보기
Erickson Charles R. (Fremont CA) Hung Lawrence Cy-Wei (Los Gatos CA), Method and structure for loading data into several IC devices.
상세보기
Aldebert Jeane-Paul,FRX ; Basso Claude,FRX ; Calvignac Jean,FRX ; Chemla Paul,FRX ; Orsatti Daniel,FRX ; Verplanken Fabrice,FRX ; Zunino Jean-Claude,FRX, Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device.
상세보기
Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
상세보기
Carter William S. (Santa Clara CA), Microprocessor oriented configurable logic element.
상세보기
Lyke James C., Molecular field programmable gate array.
상세보기
Dhong Sang Hoo ; Silberman Joel Abraham, Multifunctional macro.
상세보기
Agrawal Om (San Jose CA), Multiple array customizable logic device.
상세보기
Agrawal Om (San Jose CA), Multiple array customizable logic device.
상세보기
Agrawal Om P. (San Jose CA) Landers George H. (Mountain View CA) Schmitz Nicholas A. (Cupertino CA) Moench Jerry D. (Austin TX) Ilgenstein Kerry A. (Austin TX), Multiple array high performance programmable logic device family.
상세보기
Pickett Scott K. (San Jose CA) Luich Thomas M. (Campbell CA) Swift ; IV Arthur L. (Welches OR), Multiple page programmable logic architecture.
상세보기
Mitchell ; Jr. Ralph C. (Kingston NY), PLA With time division multiplex feature for improved density.
상세보기
Ogura Setsuo (Takasaki JPX) Kondo Shizuo (Takasaki JPX) Minamimura Eiji (Takasaki JPX) Furihata Makoto (Tamamura JPX), PLA with forward-conduction bipolar “and”array and I²L “OR”array.
상세보기
Takata Akira (Amagasaki JPX) Obata Takeo (Osaka JPX), Partially enabled programmable logic device.
상세보기
Birkner ; John M. ; Chua ; Hua-Thye, Programmable array logic circuit.
상세보기
Wong, Sing Y.; Birkner, John M., Programmable array logic circuit with shared product terms.
상세보기
Lebel Ronald J. (Los Angeles CA), Programmable clock generator.
상세보기
Burton Dennis A. (Linthicum MD) Goble Wendy L. (Gambrills MD) Morelli Robert D. (Columbia MD) Phelps Thomas B. (Laurel MD), Programmable configurable logic memory.
상세보기
Nakaya Shogo,JPX, Programmable function block.
상세보기
Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure.
상세보기
Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.
상세보기
Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.
상세보기
Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Programmable gate array with improved interconnect structure, input/output structure and configurable logic block.
상세보기
Agrawal Om P. (San Jose CA) Wright Michael J. (Boulder CO), Programmable gate array with logic cells having symmetrical input/output structures.
상세보기
Anderson Robert E. (Beaverton OR), Programmable high speed state machine with sequencing capabilities.
상세보기
Norman Kevin A. (Belmont CA), Programmable integrated circuit micro-sequencer device.
상세보기
Fuchs Peter (Munich DEX) Mueller-Glaser Klaus (Neuried DEX) Schuett Dieter (Munich DEX) Wach Wolfgang (Oberschleissheim DEX), Programmable logic array.
상세보기
Sunter Stephen K. (Nepean CAX) Afek Yachin (Nepean CAX), Programmable logic array.
상세보기
Weinberger Arnold (Poughkeepsie NY), Programmable logic array adder.
상세보기
Sugiyama Yoshi (Tokorozawa JPX) Kataoka Keisuke (Higashiyamato JPX), Programmable logic array arrangement.
상세보기
Shima Kazumasa (Tokyo JPX) Kawasaki Syunpei (Nakano JPX) Kubo Takashige (Hachioji JPX), Programmable logic array circuit with a decreased number of product terms.
상세보기
Hartmann Robert F. (San Jose CA) Chan Yiu-Fai (Saratoga CA) Frankovich Robert (Cupertino CA) Ou Jung-Hsing (Sunnyvale CA), Programmable logic array device using EPROM technology.
상세보기
Hartmann Robert F. (San Jose CA) Wong Sau-Ching (Hillsborough CA) Chan Yiu-Fai (Saratoga CA) Ou Jung-Hsing (Sunnyvale CA), Programmable logic array device using EPROM technology.
상세보기
Hartmann Robert F. (San Jose CA) Wong Sau-Ching (Hillsborough CA) Chan Yiu-Fai (Saratoga CA) Ou Jung-Hsing (Sunnyvale CA), Programmable logic array device using EPROM technology.
상세보기
Glaeser Winfried (Munich DEX) Schuett Dieter (Munich DEX), Programmable logic array for carrying out logic operations of binary input signals.
상세보기
Nanya Takashi (Tokyo JPX) Tanaka Takeo (Tokyo JPX), Programmable logic array for generating EOR sums of input signals.
상세보기
Kondou Harufusa (Hyogo JPX) Kuranaga Hiroshi (Hyogo JPX), Programmable logic array having a changeable logic structure.
상세보기
Shizukuishi Makoto (Kanagawa JPX) Brauer Dave W. (Tokyo JPX), Programmable logic array having feedback flip-flops connected between a product array\s inputs and its outputs.
상세보기
Kollaritsch Paul W. (Hazlet NJ), Programmable logic array interconnection matrix.
상세보기
Birkner John (Sunnyvale CA) Chua Hua T. (Los Altos Hills CA) Chan Andrew K. L. (Milpitas CA) Chan Albert (San Jose CA), Programmable logic array with added array of gates and added output routing flexibility.
상세보기
Taniai Takayoshi (Kawasaki JPX) Saitoh Tadashi (Kawasaki JPX) Tanaka Yasuhiro (Koshigaya JPX), Programmable logic array with reduced power consumption.
상세보기
Gotze, Volkmar; Schutt, Dieter, Programmable logic array with self correction of faults.
상세보기
Chung Randall M. (Laguna Niguel CA) Masters Bradley S. (Chino CA), Programmable logic array with single clock dynamic logic.
상세보기
Satake Shozo (Hadano JPX), Programmable logic array, including an arrangement for invalidating faulty and term outputs.
상세보기
Cukier Maurice (Vence FRX), Programmable logic arrays.
상세보기
Young,Steven P., Programmable logic block having lookup table with partial output signal driving carry multiplexer.
상세보기
Fujioka Takuro (Minoo JPX) Takata Akira (Amagasaki JPX), Programmable logic device.
상세보기
Takata Akira (Amagasaki JPX), Programmable logic device.
상세보기
Takata Akira (Toyonaka JPX) Fujii Koichi (Toyonaka JPX), Programmable logic device having plural programmable function cells.
상세보기
Young Michele (San Francisco CA) Shankar Kapil (San Jose CA), Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circ.
상세보기
Shankar Kapil (San Jose CA) Agrawal Om P. (San Jose CA) Mubarak Fares (Fremont CA) Young Michele (San Francisco CA), Programmable logic device with observability and preloadability for buried state registers.
상세보기
Williams David G. (Portland ME), Programmable logic device with programmable signal inhibition and inversion means.
상세보기
Veenstra Kerry S. (Concord CA), Programmable logic storage element for programmable logic devices.
상세보기
Breuninger Robert K. (Garland TX), Programmable sequence generator.
상세보기
Ogawa Katsuhiko (Yokohama JPX) Horiguchi Shinju (Yokosuka JPX), Programmable sequential logic circuit devices.
상세보기
Thierbach Mark E. (Lincroft NJ), Programmed logic array with two-level control timing.
상세보기
Page David W. (San Diego CA) Peterson LuVerne R. (San Diego CA), Re-programmable PLA.
상세보기
Howley Frank E. (Poughkeepsie NY) Jones John W. (Winchester NY EN) Logue Joseph C. (Poughkeepsie NY), Reconfigurable logic array.
상세보기
Alan David Marshall GB; Anthony Stansfield GB; Jean Vuillemin FR, Reconfigurable processor devices.
상세보기
Marshall, Alan David; Stansfield, Anthony; Vuillemin, Jean, Reconfigurable processor devices.
상세보기
Hanrahan Shaila ; Phillips Christopher E., Reconfigurable program sum of products generator.
상세보기
Chen, George K., Registers for 2-D matrix processing.
상세보기
Tanaka Mamoru (5-16-7 Higashi-jujo ; Kita-ku ; Tokyo ; 114 JPX), Rewritable programmable logic array.
상세보기
Cox Dennis T. (Kingston NY) Devine William T. (Ulster Park NY) Kelly Gilbert J. (Red Hook NY), Segmented parallel rail paths for input/output signals.
상세보기
Gaiser Thomas A. (Salem NH), Self precharging static programmable logic array.
상세보기
Maeda Shyunji (Kanagawa JPX) Wakamatsu Masataka (Kanagawa JPX), Semiconductor integrated circuit including an arbitrate circuit for giving priority to a plurality of request signals.
상세보기
Mahant-Shetti Shivaling S. (Richardson TX) Swamy Shobana (Los Angeles CA), Single integrated circuit having both a memory array and an arithmetic and logic unit (ALU).
상세보기
Tu George K. (Rolling Hills CA) Mager George E. (Manhattan Beach CA) Baker Lamar T. (Manhattan Beach CA) Markle Robert E. (Palos Verdes CA), Split programmable logic array.
상세보기
Patil Suhas S. (Salt Lake City UT), Storage/logic array.
상세보기
Blahut Donald E. (Holmdel NJ) Harrison Marc L. (Morganville NJ) Killian Michael J. (Eatontown NJ) Thierbach Mark E. (Lincroft NJ), Stored-program control machine.
상세보기
Harrison Marc L. (Morganville NJ), Structured logic array.
상세보기
Seawright, J. Andrew, System and method for control synthesis using a reachable states look-up table.
상세보기
Baxter,Michael A., System and method for dynamic reconfigurable computing using automated translation.
상세보기
Muehldorf Eugen Igor (Potomac MD), Time split array logic element and method of operation.
상세보기
Jones John W. (Poughkeepsie NY), Universal LSI array logic modules with integral storage array and variable autonomous sequencing.
상세보기
Guterman Daniel C. (Plano TX), User reprogrammable programmed logic array.
상세보기
Baskett Ira E. (Tempe AZ), Writable array logic.
상세보기
Greer ; Jr. W. T. (Plano TX) Laczko Frank L. (Plano TX), Writable logic array.
상세보기

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Depth-optimal mapping of logic chains in reconfigurable fabrics 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

이 특허에 인용된 특허 (158)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

이 특허와 함께 이용한 콘텐츠

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

연합인증

Depth-optimal mapping of logic chains in reconfigurable fabrics 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허에 인용된 특허 (158)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

이 특허와 함께 이용한 콘텐츠

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트