최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0471009 (2012-05-14) |
등록번호 | US-8664042 (2014-03-04) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 0 인용 특허 : 320 |
A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using fi
A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.
1. A method to construct configurable systems, the method comprising: providing a first configurable system comprising a first die and a second die, wherein the connections between said first die and said second die comprise through-silicon-via (“TSV”),wherein said first die is diced from a first wa
1. A method to construct configurable systems, the method comprising: providing a first configurable system comprising a first die and a second die, wherein the connections between said first die and said second die comprise through-silicon-via (“TSV”),wherein said first die is diced from a first wafer using first dice lines;providing a second configurable system comprising a third die and a fourth die, wherein the connections between said third die and said fourth die comprise through-silicon-via (“TSV”),wherein said third die is diced from a third wafer using third dice lines; andprocessing said first wafer and said third wafer utilizing at least 20 masks that are the same; wherein said first dice lines are substantially different than said third dice lines, andwherein said second die comprises a configurable I/O to connect said first configurable system to external devices. 2. The method to construct configurable systems according to claim 1, wherein said first die is a field programmable gate array (FPGA) die. 3. The method to construct configurable systems according to claim 1, wherein said fourth die comprises a configurable I/O die. 4. The method to construct configurable systems according to claim 1, wherein said first die comprises a configurable memory die. 5. The method to construct configurable systems according to claim 1, wherein said first die comprises a repeating array of functional units. 6. The method to construct configurable systems according to claim 1, wherein said first die comprises a repeating array of functional units, wherein each of said functional units comprises a micro controller unit (MCU). 7. The method to construct configurable systems according to claim 1, wherein said first die comprises unused dice lines. 8. The method to construct configurable systems according to claim 1, wherein said diced comprises an etch step to define dice lines as a post process step. 9. A method to construct configurable systems, the method comprising: providing a first configurable system comprising a first die and a second die;wherein the connections from said first die to said second die comprise through-silicon vias (TSV),wherein said first die is diced from a first wafer using first dice lines,wherein said first dice lines are selected from a plurality of predefined potential dice lines, andwherein said first die comprises unused dice lines, andwherein said second die comprises unused dice lines,providing a second configurable system comprising a third die and a fourth die,wherein the connections between said third die and said fourth die comprise through-silicon-vias (“TSV”),wherein said third die is diced from a third wafer using third dice lines; andprocessing said first wafer and said third wafer utilizing at least 20 masks that are the same;wherein said first dice lines are substantially different than said third dice lines. 10. A method to construct configurable systems according to claim 9, wherein said second die comprises a configurable memory. 11. A method to construct configurable systems according to claim 9, wherein said first die is a field programmable gate array (FPGA) die. 12. A method to construct configurable systems according to claim 9, wherein said first die comprises a configurable I/O die. 13. A method to construct configurable systems, the method comprising: providing a first configurable system comprising a first die and a second die, wherein the connections between said first die and said second die comprise through-silicon-via (“TSV”), wherein said first die is diced from a first wafer using first dice lines;providing a second configurable system comprising a third die and a fourth die, wherein the connections between said third die and said fourth die comprise through-silicon-via (“TSV”),wherein said third die is diced from a third wafer using third dice lines; andprocessing said first wafer and said third wafer utilizing at least 20 masks that are the same; wherein said first dice lines are substantially different than said third dice lines, andwherein said second die comprises a configurable I/O to connect said first configurable system to external devices, andwherein said fourth die comprises a SerDes circuit. 14. The method to construct configurable systems according to claim 13, wherein said first die is a field programmable gate array (FPGA) die. 15. The method to construct configurable systems according to claim 13, wherein said fourth die comprises a configurable I/O die. 16. The method to construct configurable systems according to claim 13, wherein said first die comprises a configurable memory die. 17. The method to construct configurable systems according to claim 13, wherein said first die comprises a repeating array of functional units. 18. The method to construct configurable systems according to claim 13, wherein said first die comprises a repeating array of functional units, and wherein each of said functional units comprises a micro controller unit (MCU). 19. The method to construct configurable systems according to claim 13, wherein said diced comprises an etch step to define dice lines as a post process step. 20. The method to construct configurable systems according to claim 13, wherein said first die comprises unused dice lines.
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