최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0041584 (2008-03-03) |
등록번호 | US-8667443 (2014-03-04) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 60 인용 특허 : 504 |
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and com
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.
1. A method for defining a multiple patterned cell layout for use in an integrated circuit design, comprising: defining a layout for a level of a cell, the layout defined by a number of linear-shaped layout features commonly oriented to extend lengthwise in a same direction, each of the number of li
1. A method for defining a multiple patterned cell layout for use in an integrated circuit design, comprising: defining a layout for a level of a cell, the layout defined by a number of linear-shaped layout features commonly oriented to extend lengthwise in a same direction, each of the number of linear-shaped layout features devoid of a substantial change in direction along its length;splitting the layout into a plurality of sub-layouts for the level of the cell, such that each of the number of linear-shaped layout features in the layout is allocated to any one of the plurality of sub-layouts, and wherein each of the plurality of sub-layouts is defined on a separate mask, and wherein each separate mask for the plurality of sub-layouts corresponds to a same portion of the level of the cell; andstoring the plurality of sub-layouts for the level of the cell in a digital data format on a data storage device. 2. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, wherein a size of the linear-shaped layout features and a spacing between adjacent ones of the linear-shaped layout features in the layout for the level of the cell are outside a fabrication capability of a given semiconductor fabrication process, and wherein the size of the linear-shaped layout features and a spacing between adjacent ones of the linear-shaped layout features in each sub-layout for the level of the cell are within the fabrication capability of the given semiconductor fabrication process. 3. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, wherein each sub-layout for the level of the cell is to be fabricated separately within a common area of a chip. 4. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, wherein the cell represents an abstraction of a logic function and encapsulates lower-level integrated circuit layouts for implementing the logic function. 5. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, wherein sidewardly adjacent ones of the linear-shaped layout features in the layout for the level of the cell are allocated to different sub-layouts. 6. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, wherein linear-shaped layout features sharing a common electrical function in the layout for the level of the cell are allocated to a common sub-layout. 7. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 6, wherein linear-shaped layout features for active region contacts are commonly allocated to one sub-layout, and wherein linear-shaped layout features for gate contacts are commonly allocated to another sub-layout. 8. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, wherein every other linear-shaped layout feature in the layout for the level of the cell is allocated to a common sub-layout, wherein an identification of every other linear-shaped layout feature is made in accordance with a direction perpendicular to a lengthwise traversal direction of the linear-shaped layout features across the cell. 9. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, further comprising: repeating the defining, splitting, and storing for a number of levels of the cell. 10. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, further comprising: defining a sub-layout sequence for the level of the cell by allocating an edge layout feature of the level of the cell to a particular sub-layout and by allocating sidewardly adjacent ones of the linear-shaped layout features relative to a direction extending across the level of the cell away from the edge layout feature according to a fixed ordering of the plurality of sub-layouts for the level of the cell, wherein a number of possible sub-layout sequences for the level of the cell is equal to the number of the plurality of sub-layouts for the level of the cell. 11. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 10, further comprising: generating a number of variants of the cell, wherein each variant of the cell is defined by a unique combination of sub-layout sequences applied across levels of the cell; andstoring each variant of the cell in a cell library on a data storage device for storing data to be read by a computer system. 12. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, further comprising: performing process compensation technique (PCT) processing on each sub-layout to generate a PCT processed version of each sub-layout; andstoring the PCT processed version of each sub-layout in a cell library on a data storage device for storing data to be read by a computer system. 13. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 12, wherein the PCT processing is performed on a given sub-layout by defining a lithographic buffer region around the given sub-layout, wherein the lithographic buffer region is defined to include a number of features that simulate a neighborhood of the given sub-layout around the cell when placed on a chip. 14. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, wherein the substantial change in direction of a given linear-shaped layout feature exists when a width of the given linear-shaped layout feature changes at any point thereon by more than 50% of a nominal width of the given linear-shaped layout feature along its entire length. 15. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 1, wherein the substantial change in direction of a given linear-shaped layout feature exists when a width of the given linear-shaped layout feature changes from any first location on the given linear-shaped layout feature to any second location on the given linear-shaped layout feature by more that 50% of the width of the given linear-shaped layout feature at the first location. 16. A method for creating a cell library for multiple patterning of a chip layout, comprising: defining a cell to include a number of levels having a respective linear layout defined by a number of linear-shaped layout features commonly oriented to extend lengthwise in a same direction, each of the number of linear-shaped layout features devoid of a substantial change in direction along its length, wherein the cell represents an abstraction of a logic function and encapsulates lower-level integrated circuit layouts for implementing the logic function;splitting the respective linear layout of a given level of the cell into a plurality of sub-layouts, such that each of the number of linear-shaped layout features in the respective linear layout of the given level of the cell is allocated to any one of the plurality of sub-layouts, and wherein each of the plurality of sub-layouts is defined on a separate mask, and wherein each separate mask for the plurality of sub-layouts corresponds to a same portion of the given level of the cell; andstoring a definition of the cell in a cell library in a digital data format on a data storage device, wherein the definition of the cell includes the plurality of sub-layouts associated with the given level of the cell. 17. A method for creating a cell library for multiple patterning of a chip layout as recited in claim 16, further comprising: generating a number of variants of the cell, wherein each variant of the cell is defined by a unique combination of sub-layout sequences applied across one or more levels of the cell, wherein a sub-layout sequence for a particular level of the cell is defined by allocating an edge layout feature of the particular level of the cell to a first sub-layout and by allocating sidewardly adjacent ones of the linear-shaped layout features relative to a direction extending across the particular level of the cell away from the edge layout feature according to a fixed ordering of the plurality of sub-layouts for the particular level of the cell, wherein a number of possible sub-layout sequences for the particular level of the cell is equal to the plurality of sub-layouts into which the particular level of the cell is split; andstoring each variant of the cell in the cell library on the data storage device. 18. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 16, further comprising: performing process compensation technique (PCT) processing on each sub-layout to generate a PCT processed version of each sub-layout; andstoring the PCT processed version of each sub-layout in the cell library on the data storage device. 19. A method for defining a multiple patterned cell layout for use in an integrated circuit design as recited in claim 16, wherein each linear layout prior to being split into the plurality of sub-layouts is outside a fabrication capability of a given semiconductor fabrication process, and wherein each of the plurality of sub-layouts is within the fabrication capability of the given semiconductor fabrication process. 20. A method for designing an integrated circuit for fabrication, comprising: placing a plurality of cells together on a chip layout to satisfy a netlist of an integrated circuit, wherein the plurality of cells are selected from a cell library for multiple patterning of the chip layout,wherein each of the plurality of cells includes a common level having a respective linear layout defined by a number of linear-shaped layout features commonly oriented to extend lengthwise in a same direction, each of the number of linear-shaped layout features devoid of a substantial change in direction along its length,wherein each linear layout is split into a plurality of sub-layouts such that each linear-shaped layout feature in each linear layout is allocated to any one of the plurality of sub-layouts, and such that linear-shaped layout features allocated to a given sub-layout form a consistent pattern within the common level of a given cell,wherein the plurality of cells are placed together such that the consistent pattern of linear-shaped layout features formed by the given sub-layout within the common level extends in an uninterrupted manner across the plurality of cells, andwherein the extension of the consistent pattern of linear-shaped layout features formed by the given sub-layout across the plurality of cells defines a portion of a chip-wide mask layout for the common level,wherein each sub-layout is defined on a separate chip-wide mask layout for the common level; andstoring the chip-wide mask layout for the common level in a digital data format on a data storage device. 21. A method for designing an integrated circuit for fabrication as recited in claim 20, wherein every other linear-shaped layout feature in each linear layout is allocated to a common sub-layout, wherein every other linear-shaped layout feature is defined relative to a direction extending perpendicular to a lengthwise traversal direction of the linear-shaped layout features across the common level. 22. A method for designing an integrated circuit for fabrication as recited in claim 20, wherein each chip-wide mask layout is to be independently fabricated in a co-aligned manner on the common level. 23. A set of masks for fabricating a common level of a semiconductor chip, comprising: a first mask having an area defined to include a first number of linear-shaped layout features commonly oriented to extend lengthwise in a same direction, and wherein each of the first number of linear-shaped layout features is devoid of a substantial change in its lengthwise traversal direction across the first mask, wherein the first number of linear-shaped layout features form a first sub-layout, wherein the first sub-layout defines a first portion of one or more cells, wherein each of the one or more cells represents an abstraction of a logic function and encapsulates lower-level integrated circuit layouts for implementing the logic function; anda second mask having an area defined to include a second number of linear-shaped layout features, wherein the second number of linear-shaped layout features are commonly oriented to extend lengthwise in the same direction as the first number of linear-shaped layout features, and wherein each of the second number of linear-shaped layout features is devoid of a substantial change in its lengthwise traversal direction across the second mask, wherein the area of the second mask is to be aligned with the area of the first mask, wherein the second number of linear-shaped layout features form a second sub-layout, and wherein the second sub-layout defines a second portion of the one or more cells. 24. A set of masks for fabricating a common level of a semiconductor chip as recited in claim 23, wherein the second number of linear-shaped layout features are interleaved with the first number of linear-shaped layout features when the area of the second mask is aligned with the area of the first mask. 25. A set of masks for fabricating a common level of a semiconductor chip as recited in claim 23, further comprising: a third mask having an area defined to include a third number of linear-shaped layout features, the third number of linear-shaped layout features oriented to be substantially perpendicular to both the first and second number of linear-shaped layout features when the area of the third mask is aligned with the areas of the first and second masks, wherein the third number of linear-shaped layout features are defined to provide for cutting of a portion of the first and second number of linear-shaped layout features so as to segment the first and second number of linear-shaped layout features to enable electrical connectivity necessary for the logic function of each of the one or more cells. 26. A set of masks for fabricating a common level of a semiconductor chip as recited in claim 25, wherein the first number of linear-shaped layout features is defined to extend continuously across the area of the first mask, and wherein the second number of linear-shaped layout features is defined to extend continuously across the area of the second mask.
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