IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0564309
(2012-08-01)
|
등록번호 |
US-8674494
(2014-03-18)
|
우선권정보 |
KR-10-2011-0088094 (2011-08-31) |
발명자
/ 주소 |
- Nam, Tae-Duk
- Kim, Jin-Ho
- Kim, Hyuk-Su
- Kim, Hyoung-Suk
- Lee, Tae-Young
|
출원인 / 주소 |
- Samsung Electronics Co., Ltd.
|
대리인 / 주소 |
Myers, Bigel Sibley & Sajovec P.A.
|
인용정보 |
피인용 횟수 :
3 인용 특허 :
54 |
초록
▼
A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging
A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate.
대표청구항
▼
1. A semiconductor package, comprising: a substrate;a first semiconductor chip on the substrate;a support plate on the substrate;a first electrically conductive connection between the first semiconductor chip and the support plate, wherein the first electrically conductive connection is configured t
1. A semiconductor package, comprising: a substrate;a first semiconductor chip on the substrate;a support plate on the substrate;a first electrically conductive connection between the first semiconductor chip and the support plate, wherein the first electrically conductive connection is configured to provide electrical connection between the first semiconductor chip and the substrate; anda chip stack on the support plate and on the first semiconductor chip, wherein the chip stack includes a plurality of second semiconductor chips, a first adhesion layer, and a second adhesion layer,wherein the first adhesion layer is between a first of the plurality of second semiconductor chips and the support plate and between the first of the plurality of second semiconductor chips and the first semiconductor chip, wherein the second adhesion layer is between the first of the plurality of second semiconductor chips and a second of the plurality of second semiconductor chips, wherein the first adhesion layer is thicker than the second adhesion layer, wherein the first electrically conductive connection penetrates a portion of the first adhesion layer between the first semiconductor chip and the first of the plurality of second semiconductor chips, wherein the first adhesion layer is in direct contact with the first of the plurality of second semiconductor chips, the support plate, and the first semiconductor chip, and wherein the first adhesion layer has a thickness between the first of the plurality of second semiconductor chips and the support plate and between the first of the plurality of second semiconductor chips and the first semiconductor chip that is substantially uniform. 2. The package of claim 1, wherein the first adhesion layer has substantially a same width as the first of the plurality of second semiconductor chips. 3. The package of claim 1, wherein the support plate is a first support plate, the package further comprising: a second support plate spaced apart from the first support plate, wherein the first semiconductor chip is between the first and second support plates, and wherein the second support plate is between the first of the plurality of second semiconductor chips and the substrate. 4. The package of claim 1, wherein the support plate is a dummy chip having substantially a same thickness as the first semiconductor chip. 5. The package of claim 1, wherein the support plate and the first semiconductor chip have top surfaces that are substantially co-planar. 6. The package of claim 1, wherein the first and second of the plurality of second semiconductor chips of the chip stack are offset-aligned in a first direction parallel to a surface of the substrate, and wherein a third and a fourth of the plurality of second semiconductor chips of the chip stack are offset-aligned in a second direction parallel to a surface of the substrate different from the first direction. 7. The package of claim 1, wherein the first semiconductor chip is a logic chip, and wherein the plurality of second semiconductor chips are memory chips. 8. The package of claim 1, further comprising: a buffer chip between the substrate and the chip stack. 9. The package of claim 8, further comprising; a second electrically conductive connection configured to electrically connect the buffer chip to the substrate. 10. The package of claim 9, wherein the first adhesion layer is between the first of the plurality of second semiconductor chips and the buffer chip, and wherein the second electrically conductive connection penetrates a portion of the first adhesion layer between the first of the plurality of second semiconductor chips and the buffer chip. 11. The package of claim 1, wherein the first electrically conductive connection includes a wire bond. 12. A semiconductor package, comprising: a substrate;a first semiconductor chip on the substrate;a first electrically conductive connection configured to electrically connect the first semiconductor chip to the substrate;at least one support plate on the substrate;a first chip stack on the support plate and on the first semiconductor chip, wherein the first chip stack includes a plurality of second semiconductor chips, a first adhesion layer, and a second adhesion layer,a second electrically conductive connection configured to sequentially connect the plurality of second semiconductor chips, and to connect a first of the plurality of second semiconductor chips to the substrate; anda second chip stack on the first chip stack, wherein the second chip stack includes a plurality of third semiconductor chips, a third adhesion layer, and a fourth adhesion layer,wherein the first adhesion layer is between a first of the plurality of second semiconductor chips and the support plate and between the first of the plurality of second semiconductor chips and the first semiconductor chip, wherein the second adhesion layer is between the first of the plurality of second semiconductor chips and a second of the plurality of second semiconductor chips, wherein the third adhesion layer is between the first and second chip stacks, wherein the fourth adhesion layer is between a first and a second of the plurality of third semiconductor chips, wherein the third adhesion layer is thicker than the second adhesion layer, wherein the second electrically conductive connection penetrates a portion of the third adhesion layer between the first and second chip stacks, and wherein a sidewall of an uppermost semiconductor chip of the first chip stack is vertically aligned with a sidewall of a lowermost semiconductor chip of the second chip stack. 13. The package of claim 12, wherein the plurality of second semiconductor chips are sequentially stacked and sequentially offset-aligned in a first direction parallel to a surface of the substrate, and wherein the plurality of third semiconductor chips are sequentially stacked and sequentially offset-aligned in a second direction parallel to the surface of the substrate different from the first direction. 14. The package of claim 13, wherein the second electrically conductive connection is spaced apart from the second adhesion layer. 15. A semiconductor package comprising: a packaging substrate;a first semiconductor chip on the packaging substrate;a support plate on the packaging substrate, wherein the support plate is spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate;a second semiconductor chip on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate;an adhesion layer bonding the second semiconductor chip to the first semiconductor chip and bonding the second semiconductor chip to the support plate; andan electrical coupling between the first semiconductor chip and the packaging substrate, wherein at least a portion of the electrical coupling is physically located directly between the second semiconductor chip and the packaging substrate so that the electrical coupling penetrates a portion of the adhesion layer directly between the first and second semiconductor chips, wherein at least a portion of the electrical coupling is physically located directly between the second semiconductor chip and the packaging substrate in a direction perpendicular with respect to the surface of the packaging substrate. 16. The semiconductor package of claim 15, wherein the electrical coupling comprises a wire bond extending between the first and second semiconductor chips in a direction perpendicular with respect to the surface of the packaging substrate and between the first semiconductor chip and the support plate in a direction parallel with respect to the surface of the packaging substrate. 17. The semiconductor package of claim 15 wherein the electrical coupling is a first electrical coupling, and wherein the second semiconductor chip comprises first and second surfaces with the first surface being between the second surface and the packaging substrate, the semiconductor package further comprising: a second electrical coupling between the second surface of the second semiconductor chip and the packaging substrate. 18. The semiconductor package of claim 17 wherein the first semiconductor chip comprises a semiconductor logic chip, and wherein the second semiconductor chip is a first semiconductor memory chip, the semiconductor package further comprising: a second semiconductor memory chip on the first semiconductor memory chip so that the first semiconductor memory chip is between the second semiconductor memory chip and the semiconductor logic chip, wherein the second semiconductor memory chip has first and second surfaces with the first surface of the second semiconductor memory chip between the second surface of the second semiconductor memory chip and the first semiconductor memory chip, and wherein the second electrical coupling is further between the second surface of the first semiconductor memory chip and the second surface of the second semiconductor memory chip. 19. The semiconductor package of claim 18 wherein the second electrical coupling comprises a first wire bond extending between the surface of the packaging substrate and the second surface of the first semiconductor memory chip and a second wire bond extending between the second surface of the first semiconductor memory chip and the second surface of the second semiconductor memory chip.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.