최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0189433 (2011-07-22) |
등록번호 | US-8680626 (2014-03-25) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 6 인용 특허 : 504 |
An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structur
An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.
1. An integrated circuit, comprising: a gate electrode level region including a plurality of linear-shaped conductive structures each defined to extend lengthwise in a first direction, wherein some of the plurality of linear-shaped conductive structures form one or more gate electrodes of correspond
1. An integrated circuit, comprising: a gate electrode level region including a plurality of linear-shaped conductive structures each defined to extend lengthwise in a first direction, wherein some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices; anda local interconnect conductive structure formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures,wherein at least one of the plurality of linear-shaped conductive structures does not form a gate electrode of a transistor device. 2. An integrated circuit as recited in claim 1, wherein the plurality of linear-shaped conductive structures includes a first linear-shaped conductive structure and a second linear-shaped conductive structure positioned in a side-by-side and spaced apart manner, and wherein the first linear-shaped conductive structure extends over a diffusion region of a first diffusion type, andwherein the local interconnect conductive structure is a first local interconnect conductive structure positioned between the first and second linear-shaped conductive structures so as to electrically connect to the diffusion region of the first diffusion type. 3. An integrated circuit as recited in claim 2, wherein the second linear-shaped conductive structure does not form a gate electrode of a transistor device. 4. An integrated circuit as recited in claim 2, wherein the first local interconnect conductive structure is electrically connected to either a power supply or a reference ground potential at a position away from the diffusion region of the first diffusion type. 5. An integrated circuit as recited in claim 4, wherein the first linear-shaped conductive structure extends over a diffusion region of a second diffusion type spaced apart from the diffusion region of the first diffusion type. 6. An integrated circuit as recited in claim 5, further comprising: a second local interconnect conductive structure formed between the first and second linear-shaped conductive structures so as to extend in the first direction along the first and second linear-shaped conductive structures and so as to electrically connect to the diffusion region of the second diffusion type. 7. An integrated circuit as recited in claim 6, wherein at least one of the plurality of linear-shaped conductive structures does not form a gate electrode of a transistor device. 8. An integrated circuit as recited in claim 6, wherein the second linear-shaped conductive structure does not form a gate electrode of a transistor device. 9. An integrated circuit as recited in claim 6, wherein the second local interconnect conductive structure is electrically connected to either the power supply or the reference ground potential at a position away from the diffusion region of the second diffusion type. 10. An integrated circuit as recited in claim 9, wherein the second local interconnect conductive structure is electrically connected to the reference ground potential when the first local interconnect conductive structure is electrically connected to the power supply, and wherein the second local interconnect conductive structure is electrically connected to the power supply when the first local interconnect conductive structure is electrically connected to the reference ground potential. 11. An integrated circuit as recited in claim 9, wherein the first local interconnect conductive structure is electrically connected to either the power supply or the reference ground potential at a first position as measured in the first direction outside a region of extent of the first linear-shaped conductive structure as measured in the first direction. 12. An integrated circuit as recited in claim 11, wherein the second local interconnect conductive structure is electrically connected to either the power supply or the reference ground potential at a second position as measured in the first direction outside the region of extent of the first linear-shaped conductive structure as measured in the first direction. 13. An integrated circuit as recited in claim 9, wherein the plurality of linear-shaped conductive structures includes a third linear-shaped conductive structure, the first and third linear-shaped conductive structures positioned in a side-by-side and spaced apart manner. 14. An integrated circuit as recited in claim 13, wherein at least one of the plurality of linear-shaped conductive structures does not form a gate electrode of a transistor device. 15. An integrated circuit as recited in claim 13, wherein the second linear-shaped conductive structure does not form a gate electrode of a transistor device. 16. An integrated circuit as recited in claim 15, wherein the third linear-shaped conductive structure does not form a gate electrode of a transistor device. 17. An integrated circuit as recited in claim 13, wherein adjacent ones of the first, second, and third linear-shaped conductive structures are spaced apart from each other in a second direction perpendicular to the first direction in accordance with an equal centerline-to-centerline pitch as measured in the second direction. 18. An integrated circuit as recited in claim 13, further comprising: a third local interconnect conductive structure formed between the first and third linear-shaped conductive structures so as to extend in the first direction along the first and third linear-shaped conductive structures and so as to electrically connect to both the diffusion region of the first diffusion type and the diffusion region of the second diffusion type. 19. An integrated circuit as recited in claim 18, wherein adjacent ones of the first, second, and third linear-shaped conductive structures are spaced apart from each other in a second direction perpendicular to the first direction in accordance with an equal centerline-to-centerline pitch as measured in the second direction. 20. An integrated circuit as recited in claim 19, wherein the first and third local interconnect conductive structures are spaced apart in the second direction in accordance with the equal centerline-to-centerline pitch as measured in the second direction, and wherein the second and third local interconnect conductive structures are spaced apart in the second direction in accordance with the equal centerline-to-centerline pitch as measured in the second direction. 21. An integrated circuit as recited in claim 18, further comprising: an upper interconnect level region formed above the gate electrode level region, the upper interconnect level region including a first upper interconnect conductive structure electrically connected to the third local interconnect conductive structure. 22. An integrated circuit as recited in claim 21, wherein the first upper interconnect conductive structure is electrically connected to the third local interconnect conductive structure at a position between the diffusion region of the first diffusion type and the diffusion region of the second diffusion type. 23. An integrated circuit as recited in claim 21, wherein the upper interconnect level region includes a second upper interconnect conductive structure electrically connected to the first linear-shaped conductive structure. 24. An integrated circuit as recited in claim 23, wherein the second upper interconnect conductive structure is electrically connected to the first linear-shaped conductive structure at a position between the diffusion region of the first diffusion type and the diffusion region of the second diffusion type. 25. An integrated circuit as recited in claim 23, wherein each of the first and second conductive structures are linear-shaped and positioned to extend lengthwise in a second direction perpendicular to the first direction. 26. An integrated circuit as recited in claim 25, wherein at least one of the plurality of linear-shaped conductive structures does not form a gate electrode of a transistor device. 27. An integrated circuit as recited in claim 25, wherein the second linear-shaped conductive structure does not form a gate electrode of a transistor device. 28. An integrated circuit as recited in claim 27, wherein the third linear-shaped conductive structure does not form a gate electrode of a transistor device. 29. An integrated circuit as recited in claim 9, wherein the plurality of linear-shaped conductive structures includes a third linear-shaped conductive structure and a fourth linear-shaped conductive structure, the third and fourth linear-shaped conductive structures positioned to extend lengthwise in the first direction along a same line of extent in the first direction, the third and fourth linear-shaped conductive segments separated by an end-to-end spacing region, wherein each of the third and fourth linear-shaped conductive structures is positioned in a side-by-side and spaced apart manner with regard to the first linear-shaped conductive structure. 30. An integrated circuit as recited in claim 29, wherein at least one of the plurality of linear-shaped conductive structures does not form a gate electrode of a transistor device. 31. An integrated circuit as recited in claim 29, wherein the second linear-shaped conductive structure does not form a gate electrode of a transistor device. 32. An integrated circuit as recited in claim 31, wherein the third linear-shaped conductive structure does not form a gate electrode of a transistor device. 33. An integrated circuit as recited in claim 32, wherein the fourth linear-shaped conductive structure does not form a gate electrode of a transistor device. 34. An integrated circuit as recited in claim 29, further comprising: a third local interconnect conductive structure formed between the first and third linear-shaped conductive structures and between the first and fourth linear-shaped conductive structures and through the end-to-end spacing region between the third and fourth linear-shaped conductive structures. 35. An integrated circuit as recited in claim 34, wherein the third local interconnect conductive structure is formed to electrically connect to both the diffusion region of the first diffusion type and the diffusion region of the second diffusion type. 36. An integrated circuit as recited in claim 35, further comprising: an upper interconnect level region formed above the gate electrode level region, the upper interconnect level region including a first upper interconnect conductive structure electrically connected to the third local interconnect conductive structure at a position between the diffusion region of the first diffusion type and the diffusion region of the second diffusion type. 37. An integrated circuit as recited in claim 36, wherein a portion of the third local interconnect conductive structure that extends through the end-to-end spacing region between the third and fourth linear-shaped conductive structures extends in a second direction perpendicular to the first direction beyond sides of the third and fourth linear-shaped conductive structures that are positioned away from the first linear-shaped conductive structure. 38. An integrated circuit as recited in claim 37, wherein the first upper interconnect conductive structure is electrically connected to the third local interconnect conductive structure at a position in the second direction beyond the sides of the third and fourth linear-shaped conductive structures that are positioned away from the first linear-shaped conductive structure. 39. An integrated circuit as recited in claim 36, wherein the upper interconnect level region includes a second upper interconnect conductive structure electrically connected to the first linear-shaped conductive structure. 40. An integrated circuit as recited in claim 39, wherein the second upper interconnect conductive structure is electrically connected to the first linear-shaped conductive structure at a position between the diffusion region of the first diffusion type and the diffusion region of the second diffusion type. 41. An integrated circuit as recited in claim 39, wherein each of the first and second upper interconnect conductive structures are linear-shaped and positioned to extend lengthwise in a second direction perpendicular to the first direction. 42. An integrated circuit, comprising: a gate electrode level region including first, second, and third linear-shaped conductive structures positioned in a side-by-side and spaced-apart manner such that the second linear-shaped conductive structure is positioned between the first and third linear-shaped conductive structures, wherein each of the first, second, and third linear-shaped conductive structures is formed to extend lengthwise in a first direction,wherein the second linear-shaped conductive structure extends over a diffusion region of a first diffusion type to form a gate electrode of a transistor of a first transistor type, andwherein the second linear-shaped conductive structure also extends over a diffusion region of a second diffusion type to form a gate electrode of a transistor of a second transistor type;a first local interconnect conductive structure formed between the first and second linear-shaped conductive structures so as to extend in the first direction along the first and second linear-shaped conductive structures; anda second local interconnect conductive structure formed between the second and third linear-shaped conductive structures so as to extend in the first direction along the second and third linear-shaped conductive structures,wherein one of the first and second local interconnect conductive structures is formed to electrically connect to both the diffusion region of the first diffusion type and the diffusion region of the second diffusion type. 43. An integrated circuit as recited in claim 42, wherein one of the first and second local interconnect conductive structures does not extend in the first direction past an end of the second linear-shaped conductive structure. 44. An integrated circuit as recited in claim 42, wherein each of the first, second, and third linear-shaped conductive structures has a respective first end and a respective second end, and wherein the first ends of the first, second, and third linear-shaped conductive structures are substantially aligned in the first direction, and wherein the second ends of the first, second, and third linear-shaped conductive structures are substantially aligned in the first direction. 45. An integrated circuit, comprising: a gate electrode level region including first, second, and third linear-shaped conductive structures positioned in a side-by-side and spaced-apart manner such that the second linear-shaped conductive structure is positioned between the first and third linear-shaped conductive structures, wherein each of the first, second, and third linear-shaped conductive structures is formed to extend lengthwise in a first direction,wherein the second linear-shaped conductive structure extends over a diffusion region of a first diffusion type to form a gate electrode of a transistor of a first transistor type, andwherein the second linear-shaped conductive structure also extends over a diffusion region of a second diffusion type to form a gate electrode of a transistor of a second transistor type;a first local interconnect conductive structure formed between the first and second linear-shaped conductive structures so as to extend in the first direction along the first and second linear-shaped conductive structures;a second local interconnect conductive structure formed between the second and third linear-shaped conductive structures so as to extend in the first direction along the second and third linear-shaped conductive structures; anda first upper interconnect conductive structure electrically connected to the first local interconnect conductive structure. 46. An integrated circuit as recited in claim 45, further comprising: a second upper interconnect conductive structure electrically connected to the second local interconnect conductive structure. 47. An integrated circuit as recited in claim 46, further comprising: a third local interconnect conductive structure formed between the first and second linear-shaped conductive structures so as to extend in the first direction along the first and second linear-shaped conductive structures. 48. An integrated circuit as recited in claim 47, further comprising: a third upper interconnect conductive structure electrically connected to the third local interconnect conductive structure. 49. An integrated circuit as recited in claim 48, wherein the first local interconnect conductive structure is electrically connected to a power supply. 50. An integrated circuit as recited in claim 49, wherein the third local interconnect conductive structure is electrically connected to a reference ground potential. 51. An integrated circuit as recited in claim 50, wherein the first linear-shaped conductive structure does not form a gate electrode of a transistor device. 52. An integrated circuit as recited in claim 51, wherein the third linear-shaped conductive structure does not form a gate electrode of a transistor device.
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