IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0267780
(2005-11-04)
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등록번호 |
US-8683184
(2014-03-25)
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발명자
/ 주소 |
- Lew, Stephen D.
- Karandikar, Ashish
- Gadre, Shirish
- Sijstermans, Franciscus W.
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출원인 / 주소 |
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인용정보 |
피인용 횟수 :
2 인용 특허 :
151 |
초록
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A method for implementing multi context execution on a video processor having a scalar execution unit and a vector execution unit. The method includes allocating a first task to a vector execution unit and allocating a second task to the vector execution unit. The first task is from a first context
A method for implementing multi context execution on a video processor having a scalar execution unit and a vector execution unit. The method includes allocating a first task to a vector execution unit and allocating a second task to the vector execution unit. The first task is from a first context in the second task is from a second context. The method further includes interleaving a plurality of work packages comprising the first task and the second task to generate a combined work package stream. The combined work package stream is subsequently executed on the vector execution unit.
대표청구항
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1. A method for implementing a multi context execution on a video processor having a scalar execution unit and a vector execution unit, comprising: allocating a first task to the vector execution unit, wherein the first task is from a first context;allocating a second task to the vector execution un
1. A method for implementing a multi context execution on a video processor having a scalar execution unit and a vector execution unit, comprising: allocating a first task to the vector execution unit, wherein the first task is from a first context;allocating a second task to the vector execution unit, wherein the second task is from a second context;interleaving a plurality of work packages comprising the first task and the second task resulting in a combined work package stream, wherein each work package comprises tasks allocated for the vector execution unit by control procedures executed by the scalar execution unit; andexecuting the combined work package stream on the vector execution unit, wherein the executing comprising scheduling a context switch to reduce the amount of state data to be saved and wherein the context switch is scheduled based on a work package boundary. 2. The method of claim 1, wherein the first context is from a first scalar execution unit and wherein the second context is from a second scalar execution unit. 3. The method of claim 1, wherein the first context and the second context are from a common scalar execution unit. 4. The method of claim 1, further comprising: partitioning a data cache into a first portion and a second portion;allocating the first portion to the first task and allocating the second portion to the second task; andstoring data from the first task in the first portion and storing data from the second task into the second portion. 5. The method of claim 1, further comprising: executing the combined work package stream on the vector execution unit without requiring a context switch between the first task and the second task. 6. The method of claim 1, further comprising: storing a plurality of commands comprising the first task in a command FIFO;for each of the first task commands comprising read instructions, fetching the corresponding read data from a frame buffer memory;storing a plurality of commands comprising the first task in the command FIFO; andfor each of the second task commands comprising read instructions, fetching the corresponding read data from the frame buffer memory. 7. The method of claim 6, further comprising: for each work package, ensuring the read data corresponding to the read instructions are successfully fetched from the frame buffer memory and stored in the instruction cache prior to commencing execution of the work package by the vector execution unit. 8. The method of claim 6, wherein a DMA engine is configured to fetch the read data from the frame buffer memory. 9. The method of claim 8, wherein a vector control unit is coupled to the command FIFO and is coupled to the DMA engine and is configured to control the DMA engine to fetch the read data from the frame buffer memory. 10. A video processor for implementing multi context execution and having a scalar execution unit and a vector execution unit, comprising: a memory interface for establishing communication between the video processor and a frame buffer memory;a vector execution unit coupled to the memory interface and configured to execute vector video processing operations, wherein the vector execution unit schedules a context switch to reduce the amount of state data to be saved and wherein the context switch is scheduled based on a work package boundary; anda scalar execution unit coupled to the memory interface and configured to control the vector execution unit, wherein a first task from a first context is allocated to the vector execution unit and a second task from a second context is allocated to the vector execution unit, and wherein a plurality of work packages comprising the first task and the second task are interleaved to produce a combined work package stream for execution on the vector execution unit. 11. The video processor of claim 10, wherein the first context is from a first scalar execution unit and wherein the second context is from a second scalar execution unit. 12. The video processor of claim 10, wherein the first context and the second context are from the scalar execution unit and the scalar execution unit comprises a common scalar execution unit. 13. The video processor of claim 10, further comprising: a data cache partitioned into a first portion and a second portion, wherein the first portion is allocated to the first task and the second portion is allocated to the second task, and wherein data from the first task is stored in the first portion and data from the second task is stored into the second portion. 14. The video processor of claim 10, wherein the combined work package stream is executed on the vector execution unit without requiring a context switch between the first task and the second task. 15. The video processor of claim 10, wherein, for each work package, the vector execution unit is configured to ensure the read data corresponding to the read instructions are successfully fetched from the frame buffer memory and stored in an instruction cache prior to commencing execution of the work package by the vector execution unit. 16. A system for executing multi-context video processing operations, comprising: a CPU;a video processor coupled to the CPU, comprising:a memory interface for establishing communication between the video processor and a frame buffer memory;a vector execution unit coupled to the memory interface and configured to execute vector video processing operations, wherein the vector execution unit schedules a context switch to reduce the amount of state data to be saved and wherein the context switch is scheduled based on a work package boundary; anda scalar execution unit coupled to the memory interface and configured to control the vector execution unit, wherein a first task from a first context is allocated to the vector execution unit and a second task from a second context is allocated to the vector execution unit, and wherein a plurality of work packages comprising the first task and the second task are interleaved to produce a combined work package stream for execution on the vector execution unit. 17. The system of claim 16, wherein the first context is from a first scalar execution unit and wherein the second context is from a second scalar execution unit. 18. The system of claim 16, wherein the first context and the second context are from the scalar execution unit and the scalar execution unit comprises a common scalar execution unit. 19. The system of claim 16, further comprising: a data cache partitioned into a first portion and a second portion, wherein the first portion is allocated to the first task and the second portion is allocated to the second task, and wherein data from the first task is stored in the first portion and data from the second task is stored into the second portion. 20. The system of claim 16, wherein, for each work package, the vector execution unit is configured to ensure the read data corresponding to the read instructions are successfully fetched from the frame buffer memory and stored in an instruction cache prior to commencing execution of the work package by the vector execution unit. 21. The system of claim 16, wherein the vector execution unit schedules ahead read requests of instructions and data streams of a next few executes while working on the current execute.
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