Operational cycle assignment in a configurable IC
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/455
G06F-017/50
출원번호
US-0965815
(2010-12-10)
등록번호
US-8683410
(2014-03-25)
발명자
/ 주소
Rohe, Andre
Teig, Steven
출원인 / 주소
Tabula, Inc.
대리인 / 주소
Adeli LLP
인용정보
피인용 횟수 :
0인용 특허 :
110
초록▼
Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations
Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.
대표청구항▼
1. A method for mapping an integrated circuit (“IC”) design to an IC, the design comprising a plurality of components, the method comprising: identifying a plurality of multi-path components that are each on multiple signal paths;for each component, computing, by a computer, a normalized metric valu
1. A method for mapping an integrated circuit (“IC”) design to an IC, the design comprising a plurality of components, the method comprising: identifying a plurality of multi-path components that are each on multiple signal paths;for each component, computing, by a computer, a normalized metric value that falls within a fixed numerical range to express a position of the component on a uniform scale that is used to express positions of all components with respect to each other,said computing comprising computing, for each multi-path component of a subset of the plurality of multi-path components, the normalized metric value based at least partially on a distance of the multi-path component to a start of a first signal path and a distance of the multi-path component to an end of a second signal path that is different from an end of the first signal path; andbased on the normalized metric value, assigning the component to one of a plurality of operational cycles. 2. The method of claim 1, wherein assigning the component to an operational cycle comprises: identifying a configurable circuit in the IC for configurably implementing an operation performed by the component; anddefining a configuration data set for the identified configurable circuit to implement the operation performed by the component during the operational cycle. 3. The method of claim 2, wherein the configurable circuit is a reconfigurable circuit. 4. The method of claim 1, wherein computing the normalized metric value for the multi-path component comprises: identifying a longest signal path that includes the multi-path component; andassigning the normalized metric value to the multi-path component based on a position of the multi-path component on the identified longest signal path. 5. The method of claim 4, wherein the normalized metric value is a value between zero and one. 6. The method of claim 4, wherein the position of the multi-path component on the identified longest signal path is measured at least partially in terms of a number of intervening components along a signal path. 7. The method of claim 4, wherein the position of the multi-path component on the identified longest signal path is measured at least partially in terms of an overall signal delay through intervening components along a signal path. 8. The method of claim 1, wherein components with higher normalized metric values are placed in later operational cycles. 9. A non-transitory computer readable medium storing a computer program which, when executed by at least one processor, designs an integrated circuit (“IC”) with a plurality of configurable circuits, the computer program comprising sets of instructions for: receiving a design comprising a plurality of signal paths, each signal path defined by a set of components that are communicatively coupled; andassigning, for each of a plurality of components, a component in a signal path to an operational cycle based at least partially on a metric value that is normalized over (i) a first distance value that expresses a signal delay between a source point of the signal path and the component, and (ii) a second distance value that expresses a signal delay between the component and a target point of the signal path, said normalized metric value falls within a fixed numerical range to express a position of the component on a uniform scale that is used to express relative positions of all components within the signal path. 10. The non-transitory computer readable medium of claim 9, wherein the component is in only one signal path, wherein the normalized metric value is defined as the first distance value divided by a sum of the first and second distance values. 11. The non-transitory computer readable medium of claim 10, wherein components with higher normalized metric values are placed in later operational cycles. 12. The non-transitory computer readable medium of claim 9, wherein the first distance value accounts for a first number of intervening components between the source point of the signal path and the component and the second distance value accounts for a second number of intervening components between the component and the target point of the signal path. 13. The non-transitory computer readable medium of claim 9, wherein the first and second distance values are normalized topological metric values. 14. The non-transitory computer readable medium of claim 9, wherein the plurality of configurable circuits are reconfigurable circuits. 15. The non-transitory computer readable medium of claim 9, wherein the operational cycle is a sub cycle of a user defined clock cycle. 16. The non-transitory computer readable medium of claim 9, wherein the set of instructions for assigning comprises a set of instructions for assigning an approximately equal number of components to each of a set of operational cycles. 17. A method for mapping an integrated circuit (“IC”) design to an IC, the design comprising a plurality of components, each component in one or more signal paths, the method comprising: for each particular component of the plurality of components, calculating, by a computer, a normalized metric value based at least partially on (i) a number of components along a signal path that includes the particular component and (ii) a number of components from the start of the signal path to the particular component, wherein the normalized metric value falls within a fixed numerical range to express a position of the component on a uniform scale that is used to express positions of all components with respect to each other; andassigning the plurality of components to different operational cycles based at least partially on the normalized metric values calculated for the plurality of components, wherein each of the different operational cycles corresponds to a unique range of normalized metric values. 18. The method of claim 17, wherein components with higher normalized metric values are placed in later operational cycles. 19. The method of claim 17, wherein the IC is a sub-cycle reconfigurable IC and the different operational cycles are sub-cycles of a user defined clock. 20. The method of claim 17, wherein assigning the plurality of components to different operational cycles comprises: sorting the plurality of components based on the normalized metric values of the plurality of components; andassigning an approximately equal number of components to each operational cycle. 21. The method of claim 17, wherein the normalized metric value for each particular component of the plurality of components is based at least partially on a signal path with a maximum number of components among all paths that include the particular component. 22. The method of claim 17, wherein the normalized metric value for the particular component is further based at least partially on a signal delay through components along the signal path that includes the particular component.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (110)
Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.
Azegami Kengo,JPX ; Yamashita Koichi,JPX, Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Configuration modes for a time multiplexed programmable logic device.
Albrecht, Christoph; Chong, Philip; Kuehlmann, Andreas; Sentovich, Ellen; Passerone, Roberto, Data path and placement optimization in an integrated circuit through use of sequential timing information.
Iadanza Joseph Andrew ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Field programmable memory array.
Bennett David Wayne (Louisville CO) Dellinger Eric Ford (Boulder CO) Manaker ; Jr. Walter A. (Boulder CO) Stern Carl M. (Boulder CO) Troxel William R. (Longmont CO) Young Jay Thomas (Louisville CO), Frequency driven layout and method for field programmable gate arrays.
Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriy B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Hexagonal field programmable gate array architecture.
Ashar Pranav ; Malik Sharad ; Martonosi Margaret ; Zhong Peixin, Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware.
Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic cell for field programmable gate array having optional internal feedback and optional cascade.
Norman Kevin A. ; Patel Rakesh H. ; Sample Stephen P. ; Butts Michael R., Look-up table based logic element with complete permutability of the inputs to the secondary signals.
Chiang David (Saratoga CA) Lee Napoleon W. (Fremont CA) Ho Thomas Y. (Milpitas CA) Harrison David A. (Cupertino CA) Kucharewski ; Jr. Nicholas (Pleasanton CA) Seltzer Jeffrey H. (San Jose CA), Macrocell with product-term cascade and improved flip flop utilization.
Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
Larsen Wendell Ray (Essex Junction VT) Keyser Frank Ray (Colchester VT) Worth Brian A. (Milton VT), Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows.
Fuller Christine Marie ; Hartman Steven Paul ; Millham Eric Ernest, Method and system for optimizing a critical path in a field programmable gate array configuration.
Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable function within a standard cell chip for repair of logic circuits.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC.
Bailis, Robert Thomas; Kuhlmann, Charles Edward; Lingafelt, Charles Steven; Rincon, Ann Marie, Method and system for use of an embedded field programmable gate array interconnect for flexible I/O connectivity.
Tobagi Fouad A. ; Baird Randall B. ; Gang ; Jr. Joseph Mark ; Pang Joseph W. M., Method for operating a disk storage system which stores video data so as to maintain the continuity of a plurality of vi.
Tobagi Fouad A. ; Gang ; Jr. Joseph M. ; Baird Randall B. ; Pang Joseph W. M. ; McFadden Martin J., Method for scheduling I/O transactions in a data storage system to maintain the continuity of a plurality of video stre.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Method of time multiplexing a programmable logic device.
Moore Victor S. (Pompano Beach FL) Veneski Gerard A. (Boca Raton FL) Parker Tony E. (Boca Raton FL) Rhodes ; Jr. Joseph C. (Boca Raton FL) Kraft Wayne R. (Coral Springs FL) Stahl ; Jr. William L. (Co, Microword control system utilizing multiplexed programmable logic arrays.
Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
El Gamal Abbas A. (Palo Alto CA) El-Ayat Khaled A. (Cupertino CA) Greene Jonathan W. (Palo Alto CA) Guo Ta-Pen R. (Cupertino CA) Reyneri Justin M. (Los Altos CA), Programmable interconnect architecture.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
Clinton Kim P. N. ; Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph ; Seidel Victor Paul ; Zittritsch Terrance John, Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array.
Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Kilmoyer Ralph David ; Laramie Michael Joseph, System for implementing write, initialization, and reset in a memory array using a single cell write port.
Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert Anders (San Jose CA) Wong Jennifer (Fremont CA), Time multiplexed programmable logic device.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.