IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0888093
(2013-05-06)
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등록번호 |
US-8688293
(2014-04-01)
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발명자
/ 주소 |
- Douzane, Khaled
- Le Merdy, Stephane
- Vezier, Loic
- Jullien, Pascal
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출원인 / 주소 |
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대리인 / 주소 |
Blakely Sokoloff Taylor & Zafman LLP
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인용정보 |
피인용 횟수 :
1 인용 특허 :
32 |
초록
▼
An apparatus on an integrated circuit, and method thereof, provides a real-time flexible interface between inputs from a vehicle components and outputs to the vehicle control components. The functions comprises of a programmable interconnection matrix, engine sensors and a control interface. Both en
An apparatus on an integrated circuit, and method thereof, provides a real-time flexible interface between inputs from a vehicle components and outputs to the vehicle control components. The functions comprises of a programmable interconnection matrix, engine sensors and a control interface. Both engine sensors and control functions comprise of fixed hardwired functions and a customization hardware area. The apparatus therefore provides means for flexible powertrain events control target for the next generation of low-polluting power trains of vehicles.
대표청구항
▼
1. A programmable control apparatus comprising: a programmable interconnections matrix (PIM);a plurality of sensors and/or actuators connected to the PIM;a plurality of control functions connected to the PIM; andan interface to a central processing unit (CPU) for programming control functions of the
1. A programmable control apparatus comprising: a programmable interconnections matrix (PIM);a plurality of sensors and/or actuators connected to the PIM;a plurality of control functions connected to the PIM; andan interface to a central processing unit (CPU) for programming control functions of the PIM by the CPU, such that after programming the PIM the programmable control apparatus performs at least a control function of the plurality of control functions independent of the CPU;wherein the PIM enables real-time programmable connection of the plurality of at least sensors and/or actuators to the plurality of control functions. 2. The programmable control apparatus of claim 1, wherein at least a sensor or actuator of the plurality of sensors and/or actuators is at least one of: programmable, hardwired. 3. The programmable control apparatus of claim 1, wherein the plurality of control functions comprises at least one of: a programmable control function, a hardwired control function. 4. The programmable control apparatus of claim 1, wherein the apparatus further comprises at least one of: a programmable input/output (I/O) bank, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC). 5. The programmable control apparatus of claim 1, wherein the PIM is programmable in at least one of: power on, run-time. 6. The programmable control apparatus of claim 1, wherein the programmable PIM is programmed from one of: volatile memory, non-volatile memory. 7. The programmable control apparatus of claim 1, wherein programmable PIM is able to multiplex triggers from the plurality of power train sensors or power train actuators connected to the PIM. 8. The programmable control apparatus of claim 1, wherein the interface to the CPU comprises a dual-port random access memory. 9. The programmable control apparatus of claim 8, wherein the direct memory access enables access to at least a control function of the plurality of control functions. 10. The programmable control apparatus of claim 9, wherein the control function is a programmable control function. 11. The programmable control apparatus of claim 8, wherein the dual-port random access memory provides for direct memory access to shared data between the CPU and at least a control function of the plurality of control functions. 12. The programmable control apparatus of claim 1, wherein at least a control function of the plurality of control functions provides a high timing resolution that is independent of operation of the CPU. 13. The programmable control apparatus of claim 1, wherein at least a control function of the plurality of control functions provides event concurrency that is independent of operation of the CPU. 14. The programmable control apparatus of claim 1, further comprising: at least a signal processing unit communicatively coupled to the PIM. 15. The programmable control apparatus of claim 14, wherein the at least a signal processing unit is capable of performing multiplication and addition operations. 16. A method of operation of a programmable control apparatus comprising: programming a programmable interconnection matrix (PIM) of the programmable control apparatus to create interconnections between at least a plurality of sensors and/or actuators connected to the PIM and a plurality of control functions connected to the PIM;receiving at least a signal from the at least a plurality of sensors and/or actuators;transferring the at least a signal via the PIM to at least a control function of the plurality of control functions;generating a response by the at least a control function responsive to the at least a signal to control a function by the programmable control apparatus without loading a central processing unit (CPU) connected to the programmable control apparatus. 17. The method of claim 16, wherein the PIM enables real-time programmable connection of the plurality of at least sensors and/or actuators to the plurality of control functions. 18. The method of claim 16, wherein the plurality of control functions comprises at least one of: a programmable control function, a hardwired control function. 19. The method of claim 16, wherein at least a sensor or actuator of the plurality of sensors and/or actuators is at least one of: programmable, hardwired. 20. The method of claim 16, wherein programming the PIM comprises programming the PIM in at least one of: power on, run-time. 21. The method of claim 16, wherein programming the PIM comprises programming the PIM from one of: volatile memory, non-volatile memory. 22. The method of claim 16, further comprising: sharing data between the programmable control apparatus and the CPU by a dual-port random access memory. 23. The method of claim 22, wherein sharing data is performed by enabling access to at least a control function of the plurality of control functions. 24. The method of claim 16, wherein at least a control function of the plurality of control functions provides at least one of: high timing resolution that is independent of operation of the CPU, event concurrency that is independent of operation of the CPU. 25. The method of claim 16, further comprising: performing a signal processing using at least a signal processing unit connected to the PIM responsive of the at least a signal.
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