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Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a meta

Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

대표청구항 ▼

1. A structure comprising: an HBT comprising a collector, base and emitter; wiring structures in electrical connection with the collector, base and emitter; a copper layer deposited on the wiring structures; a selective metal deposited on the copper layer, wherein the selective metal is CoWP; a FET

1. A structure comprising: an HBT comprising a collector, base and emitter; wiring structures in electrical connection with the collector, base and emitter; a copper layer deposited on the wiring structures; a selective metal deposited on the copper layer, wherein the selective metal is CoWP; a FET adjacent to the HBT; a dedicated wiring structure comprising a tungsten or tungsten lined stud contact in direct contact with the FET; and a copper wiring structure devoid of the selective metal in direct contact with the tungsten or tungsten lined stud contact, wherein: the dedicated wiring structure is on a same wiring level as the wiring structures; and the selective metal deposited on the copper layer is provided above a surface of a dielectric layer in which the copper wiring structure and the copper layer are formed therein. 2. The structure of claim 1, wherein the base comprises SiGe. 3. The structure of claim 1, wherein the wiring structures are damascene tungsten stud contacts with TiN liner. 4. The structure of claim 1, wherein the wiring structures are damascene copper stud contacts with Ta liner. 5. The structure of claim 1, wherein the wiring structures are dual damascene tungsten structures. 6. The structure of claim 1, wherein the metal is one of TaN, TaN/Ta, Ru, W, Mn and TiN. 7. The structure of claim 1, wherein the copper wiring structure is dedicated to the FET. 8. A structure comprising: a first device connected to a metal wire comprising a metal cap layer on copper wiring structures, wherein the metal cap layer is CoWP; a second device connected to another metal wire on a same level as the metal wire of the first device and being devoid of the metal cap layer on other copper wiring structure; wherein: the another metal wire comprises a tungsten or tungsten lined stud contact in direct contact with the second device; the other copper wiring structure is in direct contact with the second device: the another metal wire is on a same wiring level as the metal wire; and the metal cap layer deposited on the copper wiring structures is provided above a surface of a dielectric layer in which the copper wiring structures and the other copper wiring structure are formed therein. 9. The structure of claim 8, wherein the first device is an HBT comprising a base, emitter and collector. 10. The structure of claim 9, wherein the base comprises SiGe. 11. The structure of claim 9, wherein the second device is a FET. 12. The structure of claim 8, wherein the metal cap layer is one of TaN, TaN/Ta, Ru, W, Mn and TiN. 13. The structure of claim 1, wherein the copper layer is deposited within individual trenches over each of the wiring structures. 14. The structure of claim 13, wherein the trenches are of a different dimension than the wiring structures. 15. The structure of claim 14, wherein the selective metal deposited above the trenches in which the copper layer is deposited. 16. The structure of claim 8, wherein: the first device is an HBT;the metal wire is formed in individual vias;the copper wiring structures are formed in individual trenches, each having a dimension different than that of the via;the second device is a FET;the another metal wire is formed in another via; andthe copper wiring structures are formed in another trench with a dimension different than that of the another via. 17. The structure of claim 16, wherein the metal cap layer is deposited above the trenches in which the copper wiring structures are formed.